-
- News
- Books
Featured Books
- smt007 Magazine
Latest Issues
Current Issue
Spotlight on North America
A North America spotlight exploring tariffs, reshoring, AI demand, and supply chain challenges. Plus, insights on cybersecurity, workforce development, and the evolving role of U.S. electronics manufacturing.
Wire Harness Solutions
Explore what’s shaping wire harness manufacturing, and how new solutions are helping companies streamline operations and better support EMS providers. Take a closer look at what’s driving the shift.
Spotlight on Europe
As Europe’s defense priorities grow and supply chains are reassessed, industry and policymakers are pushing to rebuild regional capability. This issue explores how Europe is reshaping its electronics ecosystem for a more resilient future.
- Articles
- Columns
- Links
- Media kit
||| MENU - smt007 Magazine
Solder Paste Stencil Design for Optimal QFN Yield and Reliability
April 29, 2015 | Ben Gumpert, Lockheed MartinEstimated reading time: 10 minutes
These two components were selected based on results of previous testing. The QFN68 package has a very high die to body size ratio, and has performed relatively poorly in other thermal cycle tests. The QFN44 package, however, has a low die to body size ratio, and in a previous test, there were no failures after 2520 thermal cycles. This testing will investigate the ability to improve results on a ‘poorly’ performing part, as well as the potential for reducing performance on a ‘robust’ part.
To develop an idea about how the chosen experimental parameters and variation would affect test results, a simulation software package was used to predict the outcomes of the testing. Figure 2 shows the results of that simulation and the prediction of the average thermal cycle survival period for the QFN68 package at the solder joint heights to be used in this test. Results of previous testing were used as a baseline to fit the prediction results to the test vehicle used.
A 5 mil stencil was used for solder paste application with apertures similar to those shown in Figure 3, but which varied by location on the board to control the volume of solder deposited at different sites across the assembly. The volume of solder was controlled by the number and size of apertures on the center pad of the QFN/BTC footprint. The volume of solder applied to the perimeter pins was also adjusted, with the objective of creating similar solder joints on all component locations (i.e. solder joint with the same amount of toe wetting and with similar fillet shape), although the height of these joints was different from location to location. Ten different aperture patterns were used for the QFN44 package, and 14 different aperture patterns were used for the QFN68 package. Reduction of solder on the center pad ranged from 10% to 90%. These values are outside of both the minimum and maximum recommendations, but are being evaluated to observe potential trends.
Page 2 of 4
Testimonial
"We’re proud to call I-Connect007 a trusted partner. Their innovative approach and industry insight made our podcast collaboration a success by connecting us with the right audience and delivering real results."
Julia McCaffrey - NCAB GroupSuggested Items
AQUANOX A4727 and A4625 Lead KYZEN Offerings at SMTA Oregon Expo and Tech Forum
05/06/2026 | KYZENKYZEN, the global leader in innovative environmentally responsible cleaning chemistries, will exhibit at the SMTA Oregon Expo and Tech Forum scheduled to take place Thursday, May 19 at the Wingspan Event and Conference Center in Hillsboro, Oregon.
Connect the Dots: Designing for the Future of Manufacturing Reality—Surface Finish
05/07/2026 | Matt Stevenson -- Column: Connect the DotsWhen designing the complex boards that many electronic devices require to operate, designers should consider manufacturability at every step. This is my last article focused on designing for the always-evolving manufacturing reality. Choosing the right surface finish has always been important. If you are creating intricate designs with a wide variety of components, like for an ultra-high density interconnect (UHDI) board, surface finish is a critical last step.
Indium to Showcase High-Performance AI Application Solutions at SEMICON SEA 2026
05/01/2026 | Indium CorporationAs a leading provider of advanced materials solutions for today’s demanding AI applications, Indium Corporation® will feature its high-reliability product portfolio at SEMICON SEA 2026, May 5-7, in Kuala Lumpur, Malaysia.
ACCM Unveils Negative and Near-zero CTE Materials for Large-Format AI Chips
04/21/2026 | Advanced Chip and Circuit MaterialsAdvanced Chip and Circuit Materials, Inc. (ACCM) has launched two new materials: Celeritas HM50, with a negative coefficient of thermal expansion (CTE) of -8 ppm/°C to offset the positive CTE and expansion of copper with temperature on circuit boards, and Celeritas HM001, with near-zero CTE and the low-loss performance needed for high-speed signal layers to 224 Gb/s and faster in artificial intelligence (AI) circuits.
SMTA Ultra HDI Symposium, Day 2: Fragile Supply Chains, Fierce Innovation
04/14/2026 | Marcy LaRont, I-Connect007The Arizona weather yielded another beautiful day as we gathered for the second day of SMTA’s annual UHDI symposium. After the first full day discussing the role of AI in business and the how-tos of implementation, Avondale Mayor Mike Pineda kicked off day two, proud to showcase his city and to declare its important place in the continued development of the West Valley, an increasingly important area for tech and manufacturing.