Target Condition: Signal Integrity Without Borders
Elementary, Mr. Watson: PCB Education in the Midst of the Storms
Beyond Design: How Signals Survive the Hostile PCB Environment
The 5-22arr J-STD-001/Conformal Coating Material & Application Industry Assessment Task Group discussed the current status of round robin testing.
The 5-22as Task Group met to discuss an addendum to 5-22as, Space Applications Electronic Hardware Addendum to IPC J-STD-001F Requirements for Soldered Electrical and Electronic Assemblies.
The 5-22f IPC-HDBK-001 Task Group celebrated the completion of the forthcoming revision to IPC-HDBK-001, Handbook and Guide to Supplement J-STD-001, and discussed opening the document for an amendment to address changes as a result of J-STD-001F, Am 1.
The 5-23a Printed Circuit Board Solderability Specifications Task Group reviewed all comments submitted on the Amendment 1 to the J-STD-002D, including the substantial number from Jim Daggett of Raytheon.
The 5-23b Component and Wire Solderability Specification Task Group reviewed some potential changes to J-STD-003C that may just allow the people from DSCC to accept what could be the revision D of this standard.
The 5-24a Flux Specifications Task Group reviewed the SIR test method verification plan, including comparing the current J-STD-004 plan with the IEC round robin plan to determine the test board preparation procedures, specify the testing protocol and set the timing for the testing.
The 5-24b Solder Paste Task Group reviewed testing of solder balls, paste wetting and tackiness (tack) plus discussed rheometry testing using both parallel plate and spiral pump viscometers.
The 5-24c Solder Alloy Task Group discussed the addition of one more patented lead free alloy to J-STD-006; the best way to address the addition of rare earth elements to lead free alloys and then discussed three IPC TM-650 test methods that will be placed in the 5-24c TG KAVI site for additional discussion by members of the task group.
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