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Mentor Graphics Video: Automatically Unravel Complex FPGA SignalsDecember 2, 2015 | Mentor Graphics
Estimated reading time: Less than a minute
Optimizing large pin-count FPGAs is challenging. Manual optimization can take days and result in reduced quality.
This new video from Mentor Graphics shows how signal pin assignments can be automatically optimized between multiple FPGAs on the PCB while respecting pin-specific rules and constraints. Reduce the number of routing layers, minimize crossovers and overall trace lengths on the PCB, and reduce signal integrity issues for higher completion rates and shorter FPGA route times.
To watch this video, click here.
Embedding components into the multilayer PCB substrate can have many benefits, including reduced board size and improved signal integrity. However, embedded capacitance material (which is not really a component but rather part of the substrate) can improve power integrity dramatically by reducing AC impedance and generally enhancing the performance of the product. It takes up no additional space, is easy to implement (because it is compatible with standard FR-4 processes), and can be cost-effective.
In an interview at DesignCon, Gregory Miczek, global applications manager with RoBAT, discussed the company’s background and its expansion path from backplane defect analyzers to TDR testers for high-tech bare and assembled boards.
Modern high-speed and RF PCB design is an exciting field but comes with its own set of challenges. Signal integrity, performance, and crosstalk become major concerns. Designers for these types of projects need to learn how to control electromagnetic interference (EMI) and compatibility (EMC), which means utilizing some interesting math and calculations.
Electronics have profoundly impacted society, shaping how we live, communicate, work, and entertain ourselves. Nearly every aspect of our lives is affected by electronics in some way. If you want proof, sit and watch people in public; everyone is on a screen. The communication revolution alone has transformed our lives, enabling instant global connectivity. Some would argue these advances come with their distinct disadvantages.
High-speed PCB design is not as simple as sending a signal from the driver to the receiver over a transmission line. One should also consider the presence and interaction of the power distribution network (PDN) and how and where the return current flows. A logic schematic diagram masks detail crucial to the operation of unintentional signal pathways vital to the understanding of signal performance, crosstalk, and electromagnetic emissions. The PCB designer needs to be able to visualize the connectivity of the return current flow to avoid large loop areas that increase series inductance, degrade signal integrity, and increase crosstalk and electromagnetic radiation.