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Mentor Graphics Video: Automatically Unravel Complex FPGA Signals
December 2, 2015 | Mentor GraphicsEstimated reading time: Less than a minute
Optimizing large pin-count FPGAs is challenging. Manual optimization can take days and result in reduced quality.
This new video from Mentor Graphics shows how signal pin assignments can be automatically optimized between multiple FPGAs on the PCB while respecting pin-specific rules and constraints. Reduce the number of routing layers, minimize crossovers and overall trace lengths on the PCB, and reduce signal integrity issues for higher completion rates and shorter FPGA route times.
To watch this video, click here.
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Managing Energy Flow with Proper Stackup Design
02/13/2025 | Andy Shaughnessy, Design007At Design Con 2025, I had the opportunity to speak with Dan Beeker, technical director at NXP Semiconductor, about his technical session, which focused on optimizing PCB layers to best direct signal and power supply energy between these layers. In this interview, Dan discusses the complexities of board stackup and the significance of understanding dielectric layers for effective signal transmission. Dan is something of a “fields evangelist,” spreading the word about the need for designers to focus on fields, not just circuit theory. Toward the end, Dan summed up much of the design segment: Designing something that didn't make it break is not the same thing as designing it correctly.
DesignCon 2025: Stacking the Professional Deck
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Optical Transceiver Shipments Projected to Grow by 56.5% in 2025
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Keysight, KD Partner to Advance Multigigabit Optical Automotive Ethernet Testing with New Signal Analysis Capability
01/30/2025 | Keysight TechnologiesKeysight Technologies, Inc. and KD, Inc., a fabless semiconductor company, have collaborated to create a comprehensive test for Multigigabit Optical Automotive Ethernet physical layer.