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Behind the Scenes: Adcom’s TLA Award-Winning Design
May 18, 2016 | Ruth Kastner, AdcomEstimated reading time: 2 minutes
Many of you are familiar with Mentor Graphics’ Technology Leadership Award program. Adcom’s design team placed first in this year’s TLA program, taking the top spot for the category of “Computers, Blade & Servers, Memory Systems.” This article will focus on the development of that board.
This board, like most PCBs today, is a complex system designed by a multi-disciplinary team of designers, striving to bring an operational product to the market on schedule. In the case reported here, the deadline for a fabricated feasibility board was set to eight months. Within this time frame, the team had to design a product complying with demanding specs, such as the Arria 10 FPGA, PCIe 3.0, Hybrid Memory Cube (HMC) and Avago MicroPOD, as well as complying with IPC class 2 manufacturing standards.
Challenges arrived in many forms. For example, as data transfer rates are continually increasing, PCIe now runs at 8GHz. Also, operating IC voltages are lower and power requirements for various components are higher. More challenges lay in the form of small form factor of ICs and high-speed transceiver protocols. All of this requires advanced PCB fabrication technologies. The design teams need to work in union over a short design-cycle time, and provide early proof of concept. The work flow should incorporate the processes of modeling, optimization and analysis.
The outcome of this process was the delivery of an almost flawless feasibility board on the first shot. There was no need for a second version, thanks to the effort invested in overall simulation at the design and layout phase.
Requirements Implemented in Design Flow
This board was developed as a proof of concept for a very high-density data processing unit using high-speed memories and interfaces. Components included a 20 nm FPGA, advanced memory devices such as DDR4 and HMC transceivers of 15Gbps, 10Gbps and 8Gbps, and power circuits, all connected to a PCIe device. The area provided for the design was 200 mm X 200 mm with PCB thickness limited to 1.6 mm.
The major design challenges that had to be tackled were the 100A current consumption of the FPGA core, the routing of 16 HMC transceivers operating at 15GHz, and the clock tree design for optimal frequency programmability.
The design team included one FPGA designer, one librarian, three PCB designers, two layout designers, and a mechanical designer (outsourced).
To read this entire article, which appeared in the April 2015 issue of The PCB Design Magazine, click here.
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