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Electronics vs. Physics: Why Vias Don’t Get HotDecember 6, 2022 | Douglas Brooks, Consultant, and Johannes Adam, ADAM Research
Estimated reading time: 1 minute
Most of are aware that when we pass an electrical current through a trace (conductor), the trace will heat up. This temperature increase is caused by the I2R power loss dissipated in the resistance of the trace. The resistance of a copper trace is mostly determined by its geometry (cross-sectional area), and there are lots of studies trying to look at the relationship between the current down a trace (of known size) and the resulting temperature of the trace.
But the situation is much more complicated than this. There are physical properties that exist that result in helping to cool the trace. These properties are usually a combination of conduction of the heat away from the trace through the material, convection of the heat away from the trace through the air, and radiation of the heat away from the trace. A stable temperature is reached when the I2R heating equals the cooling—i.e., when the electronic and physical properties are balanced.
We have spent several (enjoyable) years collaborating on these effects. Douglas is an electrical engineer and understands electronics. Johannes is a thermodynamics physicist, and understands heat transfer. Between us we learned a lot about the thermal characteristics of vias.
Vias Don’t Get Very Hot
Traces heat because of the current through their resistance, resulting in I2R power losses. This temperature increase is caused by what we call “Joule heating”:
Joule heating is the physical effect by which the pass(age) of current through an electrical conductor produces thermal energy. This thermal energy is then evidenced through a rise in the conductor material temperature, thus the term “heating.” One can see Joule heating as a transformation between “electrical energy” and “thermal energy,” following the energy conservation principle.
We are all aware that, in general, for a given trace an increase in current through the trace will correspond to an increase in temperature of the trace. When it comes to vias, the industry guidelines have generally been to size the cross-sectional area of a via to equal that of its parent trace. Then the via will be the same temperature as the trace.
To read this entire article, which appeared in the November 2022 issue of Design007 Magazine, click here.
The "Global Copper Clad Laminates Market (by Type, Application, Reinforcement Material, & Region): Insights and Forecast with Potential Impact of COVID-19 (2023-2028)" report has been added to ResearchAndMarkets.com's offering.
The SCHMID Group, a global solution provider for the high-tech electronics, photovoltaics, glass and energy systems industries, will be exhibiting at productronica in Munich from November 14 – 17, 2023.
The topic of intrinsic copper structure has been largely neglected in discussions regarding the PCB fabrication quality control process. At face value, this seems especially strange considering that copper has been the primary conductor in all wiring boards and substrates since they were first invented. IPC and other standards almost exclusively address copper thickness with some mild attention being paid to surface structure for signal loss-mitigation/coarse properties.
At PCB West, I sat down for an interview with John Andresakis, the director of business development for Quantic Ohmega. I asked John to update us on the company’s newest materials, trends in advanced materials, and the integration of Ticer Technologies, which Quantic acquired in 2021. As John explains, much of the excitement in materials focuses on laminates with lower and lower dielectric constants.
Printed circuit board (PCB) reliability testing is generally performed by exposing the board to various mechanical, electrical, and/or thermal stimuli delineated by IPC standards, and then evaluating any resulting failure modes. Thermal shock testing is one type of reliability test that involves repeatedly exposing the PCB test board to a 288°C pot of molten solder for a specific time (typically 10 seconds) and measuring the number of cycles it takes for a board’s copper layer to separate from the organic dielectric layer. If there is no delamination, fabricators can rest assured that the board will perform within expected temperature tolerances in the real world.