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The Shaughnessy Report
By Andy Shaughnessy
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The Shaughnessy Report: Shrinking Silicon—A Warp Speed Facilitator
As we all learned by watching Star Trek, a lot of crazy things can happen at warp speed. Sure, it was great to get to Alpha Centauri in a hurry, but the Enterprise almost destroyed itself a few times when they put the pedal to the metal.
There’s just no room for error at warp speed.
Now, many PCB designers are dealing with increasing signal speeds and rise times, and a parliament of other effects—some positive, some negative—thanks to shrinking silicon. Not quite warp speed, but a lot of unpredictable things can happen when the die get tiny.
Ask yourself: Do you really understand die shrinkage?
When we researched this topic, designers and design engineers told us that smaller die sizes have been driving up signal speeds for years. But now, with today’s chipmakers making silicon increasingly smaller, things are getting, as one designer put it, “ridiculous.”
Shrinking the signal channel drives up the speed of the signal—as one EE explained, like squeezing an ice cube until it shoots out of your hand. Field effects can't be ignored when the die gets tiny. Designers and design engineers must understand EM effects and all the trade-offs involved; they have to know how to propagate each signal without overshoot or undershoot.
Material selection plays a bigger role than ever. Seemingly simple concepts such as trace length can have a big impact on the design, and crosstalk is a potential bugaboo, always lurking around the corner.
Well, why does silicon keep shrinking? There are many benefits: Smaller die reduce the current and use less power, which translates into fewer thermal issues. They’re also cheaper to produce. Like PCB fabricators cutting costs by squeezing more PCBs onto each panel, chipmakers can now stuff more chips onto every wafer.
It’s a win-win for everyone but the designers and design engineers; they must deal with rise times that leave no room for error, even in a best-case scenario. Not only must designers manage signal integrity, but EM effects as well. This is where the world is headed; you don’t want to be left behind.
So, in the February 2023 issue of Design007 Magazine, readers will learn the causes and effects of silicon shrinkage, including how to better manage EM strategies and signal integrity, as signal speeds and rise times continue their trek toward warp speed.
First, we start with a wide-ranging conversation with IPC instructor Kris Moyer, who teaches classes that touch on this topic. Kris explains all the challenges designers face with tiny die, and a few simple techniques that can save designers time and effort—if they know what they’re doing.
Next, we have a conversation with NXP Semiconductor’s Dan Beeker, who points out the need to have a firm understanding of the fundamentals of physics and EM effects when designing with shrinking silicon. Then signal integrity instructor Rick Hartley and columnist Barry Olney team up for a great article about displacement current and its role in EM energy propagation. We have a discussion with Dr. Todd Hubing, founder of LearnEMC and longtime EMC instructor, who points out the advantages and disadvantages of diminutive die, as well as a variety of mitigating tips and techniques for PCB designers and design engineers facing increased signal speeds and rise times.
We also have a host of columns from our regular contributors Matt Stevenson, John Coonrod, and Joe Fjelstad, as well as an interview with Jason Sciberras, who discusses the importance of offering optional parts in your bill of materials. With the supply chain issues we’ve had lately, this is quite a timely interview.
‘Tis the Season for Trade Shows
Speaking of timely, I just returned from IPC APEX EXPO and DesignCon. I talked to a lot of designers, and plenty of process engineers who are eager to work with designers to help preclude DFM and DFA issues before they arise. It seems like everyone downstream from design is realizing the need to keep open lines of communications with the design team. I also talked with designers who are embedded with assembly teams in the name of DFA. Are we all finally starting to communicate?
Our Real Time with… IPC APEX EXPO video interviews are available here, and my DesignCon coverage will be published in upcoming issues of Design007 Magazine and Design007 Week newsletter.
This column originally appeared in the February 2023 issue of Design007 Magazine.
More Columns from The Shaughnessy ReportThe Shaughnessy Report: Rigid-flex Design No Longer a Niche
The Shaughnessy Report: Developing a Strategy
The Shaughnessy Report: Simulation, Analysis, and AI
The Shaughnessy Report: Advanced, Complex, and Emerging Design Strategies
The Shaughnessy Report: Help Wanted
The Shaughnessy Report: Slow And Steady Wins the Race
The Shaughnessy Report: A New Materials Paradigm
The Shaughnessy Report: A Strong Start