J-STD-609 Standard:
Labeling and Marking for Harmony in a Lead-free and Tin/Lead World

Estimated reading time: 3 minutes

By Lee Wilmot, TTM Technologies; Jasbir Bath, Solectron Corporation; and Jack McCullen, Intel

After JEDEC and IPC published separate standards for labeling lead-free components and assemblies JESD-97 and IPC-1066 in 2004 and 2005, the J-STD-609 committee was created to work on a joint standard. Since March 2005, committee members have been developing the "Marking and Labeling of Components, PCBs, and PCBAs to Identify Lead, Lead-free, and Other Attributes" joint standard. The demand for a harmonized standard is high due to increased timing pressures for developing a global standard and initiatives to adapt to alternative internationally proposed standards.

In the case of J-STD-609, the standard was able to meet the needs of PCB manufacturers, component suppliers, and EMS companies to provide a workable and practical labeling and marking standard. The standard includes mandatory and optional labeling-and-marking requirements for features such as surface or terminal finish, materials, halogen-free PCB base materials, and conformal coatings. For example, for lead-free surface or terminal finishes and materials, and lead-free assembly solders, the following codes are used:

e1: tin/silver/copper (Sn/Ag/Cu SAC) e2: tin (Sn) alloys with no bismuth (Bi) or zinc (Zn), excluding SACe3: tin (Sn)e4: precious metal [e.g., silver (Ag), gold (Au), nickel/palladium (Ni/Pd), nickel/palladium/gold (Ni/Pd/Au) (no Sn)]e5: tin/zinc (Sn/Zn), tin/zinc/other (Sn/Zn/X), all other alloys containing tin (Sn) and zinc (Zn) and not containing bismuth (Bi)e6: contains bismuth (Bi)e7: low-temperature solder (≤150°C) containing indium (In) [no Bi]e8 and e9 symbols: unassigned

An example of the code for a pure-tin-coated (e3) component is shown in Figure 1. Lead-free is also defined in the standard as having a concentration of lead with a maximum concentration value of 0.1% by weight in each homogeneous material.

J-STD-609 incorporates a significant change from the two previous standards in that surface or terminal finishes, materials, and assembly solders containing lead must be marked. Since lead-containing materials are still in use for certain applications, this provision allows buyers and sellers who adopt the standard into their procurement system to identify whether PCBs, components, or assemblies contain lead. This change was considered to be a major step in a unified standard, as the paradigm shift to lead-free electronics created a need to identify not only lead-free materials, but also traditional lead-containing coatings, finishes, and solders for exempt segments, such as military and defense electronics.

The e0 marking indicates that the material or solder contains lead at concentrations above 1000 ppm. For second-level interconnect terminal finishes and materials, the standard establishes that e0 has a lead content equal to or greater than 3% by weight. Committee members agreed that it was important to explain that second-level interconnect defines the connection made by attaching a component to a PCB. This connection is external to the component, not internal. Examples of materials constituting the second-level interconnect, which are the main focus of the standard, include BGA or other area-array solder balls, thru-hole and SMT component leads, solder paste, PCB pads, and any related relevant materials, such as solder preforms.

One of the major issues in developing a uniform global marking standard was "if space permits," especially for components. J-STD-609 requires marking the surface or terminal finish and materials whenever space permits, but also provides a labeling alternative when space does not permit. Such labels can be either barcode or 2D format, and must contain minimum information such as second-level interconnect, applicable materials category code, and maximum component body temperature. Figures 2a and 2b show examples of second-level interconnect component labels that, if used, are placed or printed on the lowest-level shipping container and any ESD packaging, dry pack, or other bag or box, excluding tubes, trays, reels, or other carriers.

Rework or repair changes and any associated remarking of the assembly are also addressed by J-STD-609. While most current labeling and marking issues have been incorporated into J-STD-609, the committee knows that the one constant in the electronics industry is change. Although the standard is published, our working group will start on the next revision as implementation issues and other questions identify new labeling and marking needs. In addition, the J-STD-609 joint standard will be submitted to the relevant International Electrotechnical Commission (IEC) standard committee for global adoption.

Lee Wilmot, EHS director, TTM Technologies; Jasbir Bath, advisory process engineer, Solectron Corporation; and Jack McCullen, senior staff engineer, Intel, are co-chairs of IPC Task Group 4-34b on marking and labeling assemblies, components and devices.

J-STD-609 is now available for free download at IPC's Website. For questions on J-STD-609, contact Fern Abrams, IPC director of environmental policy, at FernAbrams@ipc.org or (703) 522-0225.