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Understanding DFM and its Role in PCB LayoutApril 14, 2015 | Rick Almeida, Downstream Technologies
Estimated reading time: 2 minutes
DFM, DRC, DFF, DFA, DFwhat? These are all terms used daily in the PCB design world regarding manufacturing analysis, and they are often used interchangeably. But what exactly is DFM and why is it such an important, but often ignored aspect of the PCB design process?
Let’s start by clarifying some terms. DFM is short for “design for manufacturability.” It is the process of arranging a PCB layout topology to mitigate problems that could be encountered during the PCB fabrication and assembly processes required to manufacture an electronic system. Addressing fabrication issues is what’s known as design for fabrication (DFF), and addressing assembly issues during design is known as design for assembly (DFA). The two together mostly make up DFM analysis—mostly.
In many cases, the term DRC, which stands for design rule checking, is also used interchangeably with DFM and creates further confusion. That’s understandable, because DRC issues detected in manufacturing can indeed have a direct impact on the manufacturability of a PCB. However, DRC is markedly different from DFF and DFA. Think of DRC as a hard pass/fail detection of a problem in a PCB. Either a problem exists or it doesn’t. In engineering, DRC is used to ensure that PCB layout connectivity accurately reflects the connectivity defined in a board’s associated schematic diagram. But connectivity is only one aspect of DRC. The “R” stands for rules. The rules are used largely to define the minimum spacing allowed between various PCB objects for the entire PCB or for individual layers, nets or areas on the PCB. In engineering, the spacing may have direct impact on circuit performance. In manufacturing, spacing may play a pivotal role in the ability to fabricate or assemble a PCB. As a result, DRC becomes a subset of DFM, but only if the rules used reflect a manufacturer’s requirements for spacing. Otherwise, DRC is used solely for electrical verification.
DFM’s two primary components, DFF and DFA, are more nuanced than DRC. While DRC detects very specific discrepancies from the intended interconnect, DFM identifies issues in the PCB topology that have the potential to create manufacturing problems. What’s more, a DRC defect will be present in every copy of the PCB built, so if there is a short missed in DRC, every PCB will contain the short, no matter how many PCBs are produced. By contrast, if the same PCB quantities contain DFM issues, problems may only manifest in some of the PCBs while others perform correctly as expected.
For example, a PCB layout containing very thin pieces of copper created in the design tool by rule would be correct per the schematic. And if spaced properly it would pass DRC. However, that same sliver, being so thin, could potentially detach on the physical PCB and inadvertently connect itself to other copper elements during assembly, thus creating shorts on some PCBs but not on others. So, the sliver would pass DRC verification, but in real-world manufacturing the sliver could cause some PCBs to fail. Without DFM, this problem would go on undetected and would result in scrap or rework.
This article originally appeared in the March 2015 issue of The PCB Design Magazine. To read this article in its entirety, click here.
There has always been pressure to reduce line and space as we have seen the bleeding edge technology go from 8 mils to 5 mils and then to 3 mils. The difference between “then” and “now” is that the prior advancements, for the most part, used the same processes, chemistry and equipment going from 8 mils to 3 mils. But going from 3 mil to sub 1 mil trace and space is a quantum leap in printed circuit board (PCB) technology that requires a whole new set of processes and materials.
In a previous column, the critical process of desmear and its necessity to ensure a clean copper surface connection was presented. Now, my discussion will focus on obtaining a void-free and tightly adherent copper plating deposit on these surfaces. After the desmear process, the task is to insure a continuous, conductive, and void-free deposit on the via walls and capture pad. Today, there are several processes that can be utilized to render vias conductive.
Panasonic’s Darren Hitchcock spoke with the I-Connect007 Editorial Team on the complexities of moving toward ultra HDI manufacturing. As we learn in this conversation, the number of shifting constraints relative to traditional PCB fabrication is quite large and can sometimes conflict with each other.
MKS’ Atotech, a leading surface finishing brand of MKS Instruments, will participate in the upcoming IPCA Expo at Bangalore International Exhibition Centre (BIEC) and showcase its latest PCB manufacturing solutions from September 13 – 15.
Flexible circuit applications can be as basic as furnishing electrical interconnect between two conventional circuit board assemblies, or to prove a platform for placing and interconnecting electronic components. During the planning and pre-design phase of the flexible circuit, there will be several material and process related questions that need to be addressed. Most flexible circuit fabricators welcome the opportunity to discuss their customers’ flexible circuit objectives prior to beginning the actual design process.