-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLevel Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
The Key to Eliminating Bad Design Data: Constant Vigilance
March 9, 2021 | I-Connect007 Editorial TeamEstimated reading time: 2 minutes
The I-Connect007 editorial team recently met with Jen Kolar and Mark Thompson of Monsoon Solutions to discuss ways to eliminate bad data from the design process, whether that be from CAD libraries, parts vendors, chip makers, or customers themselves. They key in on some problems and obstacles that allow incorrect data into the design cycle, and then highlight possible solutions.
Barry Matties: There are just so many places where you can introduce bad data into the design cycle. And as you both know, one of the biggest challenges is to get the data that you really need to be accurate right from the start. And, if it’s wrong at the beginning, it’s wrong all the way through.
Jen Kolar: It’s like any additive process, where the errors are added along the way. You have garbage in, garbage out in each step along the way. Maybe you have a thoughtful front-end designer who does a thoughtful design and gives really good input, but you have a PCB designer who’s sloppy and leaves half the detail out of the fab notes. Maybe it was good data into them, but they didn’t translate all that to the fab shop. Or maybe they had good data from one point, but you have those additive errors. Maybe there was a partial error at the beginning, but it just builds and builds, and gets worse and worse.
Matties: The thing is, if it’s good at one point, you have so many different points where it can go off the rails. It could be a combination of good data here, bad data there.
Kolar: I couldn’t agree more, and I think part of it is dependent on who’s driving the schedule in a project; a lot of times, the people driving the schedule just care that it’s started. You have management saying “Start,” so whoever is designing the project is saying, “Okay. I’m still figuring out my electrical design, but I’ve been told to put it in schematic.” You can end up with a project that takes a lot longer, costs more, and works poorer than if you’d just waited and started two months later.
Matties: And you’ll probably be doing multiple re-spins on it as well.
Kolar: Exactly. There are a lot of different sources of poor data: There’s just lack of knowledge, schedule pressure, sloppiness, and there is misinformation. There have been a number of times that we have engineers send us reference designs and say, “Just do what the reference design says.” Then we get to argue that the reference designs have nothing to do with manufacturability, and you repeat that cycle over and over. From our perspective, when you’re getting input data, ideally, you’re getting enough variants of it that you have something to validate against. Maybe I get a board file that has some of the parts loaded. Then, maybe I also have a STEP file or mechanical data that I can sanity-check against that, or the schematic, which is also going to have some callouts.
To read this entire interview, which appeared in the March 2021 issue of Design007 Magazine, click here.
Suggested Items
Real Time with… IPC APEX EXPO 2024: My Role as a Technology Solutions Director
05/02/2024 | Real Time with...IPC APEX EXPOPeter Tranitz, senior director of technology solutions at IPC, shares insights into his role as the design initiative lead. He details his advocacy work, industry support, and the responsibilities of the design initiative committee. The conversation also covers the revamping of standards, the IPC Design Competition, and the implementation of design rules in software tools.
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.
IPC's Vision for Empowering PCB Design Engineers
04/30/2024 | Robert Erickson, IPCAs architects of innovation, printed circuit board designers are tasked with translating increasingly complex concepts into tangible designs that power our modern world. IPC provides the necessary community, standards framework, and education to prepare these pioneers as they explore the boundaries of what’s possible, equipping engineers with the knowledge, skills, and resources required to thrive in an increasingly dynamic field.
On the Line With… Talks With Cadence Expert on SI/PI for PCB Designers
05/02/2024 | I-Connect007In “PCB 3.0: A New Design Methodology—SI/PI for PCB Designers,” subject matter expert Brad Griffin, Cadence Design Systems, discusses how an intelligent system design methodology can move some signal and power integrity decision-making into the physical design space, offering real-time feedback.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.