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Designer's Notebook: Heterogeneous Integration and High-density SiP Technologies

Often, our primary goal is to maximize product functionality without increasing product size. Developing a multifunction silicon-based semiconductor (system-on-chip) for a specific product application, however, requires a significant investment in both engineering and financial resources. The problem is that many of the newer generations of semiconductor die have actually increased in size, with higher I/O and terminal pitch variations that have become significantly smaller. A key goal for developers is to increase bandwidth, reduce power, minimize package profile, and control fabrication costs. The next goal is to develop a packaging technique that is not disruptive and, ideally, can utilize the existing manufacturing infrastructure.

Note: According to a survey from the International Business Strategy Corporation, the increase of design cost for each generation technology has exceeded 50% after implementing the 22 nm process. This includes the cost of EDA, design verification, IP core, tape-out, and testing. The total design cost of 7 nm process is expected to reach about $300 million and moving to the next level 3 nm process, the semiconductor cost may increase five times, up to $1.5 billion. Because of the technical limitations in yield (such as the mask size of lithography machine), the existing monolithic integration becomes unsustainable for upgrading and expanding the functions and performance.

Implementing 2.5D System-in-Packaging Technology
To meet user demands, semiconductor developers continue their efforts to increase functionality and performance with each generation of silicon-based die elements. These same developers will then need to rely on the design engineer and semiconductor package engineering specialists to support this industry segment with timely and innovative solutions that can facilitate the new product offerings. With the advances in semiconductor imaging technology, the complexity of the individual die element has increased exponentially. Package solutions developed for these more advanced product offerings must facilitate the higher density interconnect and enable redistribution of the semiconductor’s narrow pitch terminal pattern to a broader terminal format. A primary challenge for the circuit board design professional is how best to interconnect these higher I/O, very fine terminal pitch semiconductor packages.

System-in-package developers have realized that instead of the traditional monolithic integration developed for the earlier, less complex applications, adapting mature, high-yielding miniature semiconductor “chiplet” die to meet the system level criteria is more economical and can significantly reduce development time. A chiplet is an integrated circuit block that has been specifically designed to work with other similar chiplets. Clustering and interconnecting two or more associated heterogeneous or homogenous semiconductor die within the confines of a single package outline enables closer coupling and the potential for enhanced electrical performance. By positioning these smaller and less complex functional chiplets in close proximity to the monolithic processor die, interconnect distance will be minimized and power and ground distribution optimized (Figure 1).

Most of the interface between the component(s) and package substrate interconnect is confined to the silicon-based interposer platform’s surface. This, in turn, allows the terminal array on the bottom surface of the package substrate to expand to a wider pitch, simplifying the interconnect to the host circuit board substrate.

Silicon-based 2.5D Interposers
Higher I/O semiconductors, die elements, when furnished with a uniform array of raised terminals, enable direct-die attachment to the 2.5D interposer. The primary function of the interposer is to accommodate attachment and facilitate interconnect of related die elements mounted to the interposer’s surface. Some referred to this substrate as “grid transfer,” allowing the ultra-fine-pitch semiconductor die to be expanded to a wider-pitch BGA format. The interposer may also be used to re-route the terminal pattern of one manufacturer’s semiconductor to match the terminal pattern of a product having the same function developed by another manufacturer.

A secondary function is to provide a wider pitch terminal interface on the interposer lower surface to better enable signal, power and ground interface with the lower circuit density package substate. Individual die elements arranged on the 2.5D interposer, shown in Figure 2, will each have a unique function and widely diverse physical outlines.

The package substrate (most likely the BT-epoxy based or CTE matching laminate) provides additional redistribution of I/O and power/ground terminals to a JEDEC standard ball grid array pattern that will be more compatible with commercial circuit board fabrication technology.

Design Strategy for the 2.5D Interposer
A typical 2.5D interposer application supports the interconnect of one very high terminal density semiconductor or multiple related die elements. While the upper surface of the 2.5D interposer will accommodate most semiconductor redistribution and/or die-to-die interface, the primary I/O channels and power and ground terminals are moved to the bottom surface of the interposer. Although the overall circuit density of the 2.5D interposer is significantly greater than the mainstream HDI circuit board, commercial CAD tools are available to accommodate most very-high-density (VHD) interposer development activity. Developing the high-density interposer substrate can significantly enhance product performance by enabling much shorter circuit interconnects for critical signal paths. A typical 2.5D interposer for the system-in-package (SiP) applications will probably require interconnecting two or more uncased die elements (often from multiple sources) within a single package outline.

Silicon interposer materials are commonly furnished in a thin round wafer format and sized to comply with the existing semiconductor fabrication infrastructure. Metal deposition processes developed for the silicon-based interposer enable very close coupling between related die elements. The via-hole features on the die-attach side of the interposer may have a pitch in the range of 30-50 microns. Terminal features on the bottom surface are commonly “fanned-out” to a wider 150 to 300-micron pitch. The most common through-silicon-via (TSV) formation process uses a deep reactive-ion etching (DRIE) process (often referred to as the Bosch process) that can provide vias that range between 5 microns and 20 microns.

Guidelines for designing the silicon-based interposer may vary somewhat from one supplier to another, but the designer can use the data furnished in Table 1 as a baseline that can be confirmed or altered when discussing the interposer fabrication with the designated supplier.

A good deal of silicon-based 2.5D interposer products have already been produced but, to sustain a wider acceptance, there remain several logistical challenges that will need to be addressed:

• Cost effective through-silicon-via (TSV) process
• Thin wafer and panel-handling solutions
• Lack of a broad 2.5D infrastructure
• Technical training for design engineering specialists

The number of die elements to be integrated onto a single silicon-based interposer will be dependent on the size of the die elements and complexity of the die and the area available for interconnect. One to three small outline die may be considered viable for the 10 mm and 12 mm square interposer while the larger outline interposers may include mounting and interconnecting five or more die-level elements. The factors furnished in Table 2 define capability in both standard and advanced silicon-based interposer applications.

Note: The factors outlined in the above table are all subject to change as technology advances and market trends evolve.

Warning: When adopting bare, uncased die elements, the designer must consider that suppliers may need to physically alter their semiconductor design without notice. The changes may be to correct a defect or improve yield, but often, the redesign is to reduce the die outline in order to enable a greater die element population on the silicon wafer base. Although the individual die elements may continue to be furnished with a uniform terminal format, the die element outline, terminal size, and pitch will probably shrink, and if the die outline and/or terminal pattern are changed, a new interposer or package substrate will need to be developed.

Note: The content of this article is drawn from PCB Design Engineers Handbook for Surface Mount and Microelectronics by Vern Solberg.

This column originally appeared in the September 2024 issue of Design007 Magazine.