EIPC Reliability Workshop, Tamworth, UK, September 22, 2016

Estimated reading time: 17 minutes

EIPC’s reliability workshop, presented in cooperation with Amphenol Invotec, attracted a capacity audience from eight countries—some delegates having travelled from as far away as Russia—to take the opportunity to learn first-hand how to meet OEM, ODM and EMS product quality and safety requirements, and to understand how interconnection stress testing techniques could be applied to determine the reliability of multilayer PCBs.

The workshop was introduced and moderated by EIPC technical director Michael Weinhold, and delegates were welcomed by Amphenol Invotec managing director Tim Tatton, who gave a brief history of the company from its foundation in 1978 to its present position as the UK’s largest PCB manufacturer and now, as part of Amphenol, a member of the world’s second largest interconnect company. Amphenol Invotec’s accredited expertise in time critical and technologically complex HDI, flex and flex-rigid PCBs for the defence, aerospace and industrial sectors, in partnership with its counterparts in Amphenol Printed Circuit Board Technology in Nashua, New Hampshire, enabled the capability to offer a full spectrum of interconnect solutions.  

Michael Weinhold set the scene for the workshop with an overview of the global market for PCBs, the European landscape and trends in technologies and opportunities for PCB fabricators. He posed the question: Were fabricators and assemblers ready for the future, and were they ready for evolutionary, or possibly revolutionary, change?

It was clear from the geographical distribution of PCB production that the western world manufactured less than 10% of a total value estimated at 60 billion USD: “The action takes place where the money is…” But the development work was still largely done in Europe and USA, where there was continuing growth in medical, automotive and aerospace electronics.

Emerging and evolving technologies—applications requiring thermal management, for example, and PCBs with embedded devices—presented challenges to the fabricator, and trends in component miniaturisation—next generation monolithic ceramic capacitors in 008004 format, for example—presented challenges to the assembler. And reliability became an increasingly non-negotiable demand.

But how to define “reliability” in the context of present-day electronics? “Mean Time Between Failures (MTBF)” related to the days when electronic devices could be repaired, whereas nowadays devices that failed were more likely to be replaced than repaired, and this was generally true for automotive, medical and avionics as well as consumer applications. “Mean Time to Failure” was a more appropriate measure—the length of time a device could be expected to last in operation. And to be able to measure it in advance, with a way of simulating the thermal stresses of assembly and in-service operation, would enable the design and manufacture of better boards.

Emphasising the point that a successful PCB fabricator in today’s marketplace was also a trader, Weinhold’s advice to European fabricators was to understand market trends and the needs of the industry, to build on their strengths in engineering know-how, networking and communication, to sell within the capabilities of themselves and their partners in lower-cost countries, and to measure product functionality and performance. How to control product quality? How to control reliability? How to minimise risk and liability? These would be issues addressed by the workshop.

Although the PCB only accounted for between 4% and 10% of the value of an assembly, and there were many other ways in which a device could fail, interconnection failures could be initiated during assembly processes and subsequent in-service thermal cycling as a consequence of thermal expansion of the substrate material. And complex high density interconnects offered a potentially enormous number of opportunities for failure of via connections.

Interconnection stress testing (IST) was a proven technique for rapidly quantifying the robustness of via connections on even the most complex multilayer PCBs, and Weinhold invited Bill Birch, the originator and world expert, to explain and discuss process control and performance classification using IST test systems.

Well-known for his deadpan humour, Birch apologised in advance for over-running his time allocation, although no apology was necessary—his presentation, and his responses to many questions and comments, were a tribute to the depth of knowledge and analytical insight gained over almost 30 years of developing and refining techniques for interconnection stress testing. Delegates had the opportunity to learn an awful lot about what could go wrong and why, and how it could be detected, with many informative and illuminating illustrations and explanations.

Having originally devised the concept of interconnection stress testing in Digital Equipment Company (DEC) in the early 1990s, as a tool to give a quick and repeatable measure of reliability, Birch founded PWB Interconnect Solutions in 1996 as an independent company to develop and market IST as a standardised test method. Its acceptance in 2000 by IPC for inclusion in the TM-650 manual (2.6.26A) was a major step forward and there were currently more than 190 systems globally deployed and supported. The recently established partnership with UL offered additional scope for future standardisation of IST services, and PWBIS continued to cooperate with the High Density Packaging User Group (HDPUG) on a number of ongoing reliability projects and materials characterisation programmes. It was clear that IST was gaining industry-wide acceptance as a powerful and flexible tool for determining the overall reliability of PCBs. Performance criteria for IST were becoming specified in all sectors of the electronics industry, standardised coupon designs were being introduced, and a major European manufacturer of automotive electronics now required all of its suppliers to use IST to qualify HDI product and to determine the limits of their process capability.

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