Elementary, Mr. Watson: The Design Matrix—Revealing the Hidden Truths of Reality
Connect the Dots: Designing for the Future of Manufacturing Reality—Surface Finish
The Pulse: Caught in the Crosshatch—A Cautionary Tale of Detective Work
Register for Nine Dot Connects' 1/31 Webinar: Double Data Rate Memory (DDR3)
January 17, 2018 | Nine Dot ConnectsEstimated reading time: 1 minute
There’s a lot of talk about the 3rd generation of Double Data Rate memory known as DDR3. We at Nine Dot Connects have laid out several DDR3 boards in the past three months. There is quite a bit of detail to know about DDR3 design and layout and unfortunately, there is also a lot of misinformation out there. We have waded though and analyzed the literature. We wish to share our findings and understanding with you in our latest webinar series, Double Data Rate (DDR3) Shouldn't be Double Trouble.
In our two-part series on this topic, we will first cover key concepts necessary for proper signal integrity and general DDR3 design. Topics to be covered this month are:
- Brief history of the DDR concept
- Comparison between the different generations of DDR
- The signaling and timing requirements for DDR3
- Understanding match length versus match delay
- Compensating for typical routing delay
- Using the iCD Stackup Planner to assist in delay matching calculation
In part 2, we will build upon this foundation by demonstrating the practical aspects of DDR3 layout techniques.
This latest webinar, Double Data Rate (DDR3) Shouldn't be Double Trouble, is scheduled for January 31, 2018 at 2 pm Eastern Time. For more information and to register, click HERE.
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