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Our expert contributors clear up many of the miscommunication problems between PCB designers and their fab and assembly stakeholders. As you will see, a little extra planning early in the design cycle can go a long way toward maintaining open lines of communication with the fab and assembly folks.
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EIPC SpeedNews: News from the European PCB Industry
February 15, 2018 | EIPCEstimated reading time: Less than a minute

- Review: EIPC Winter Conference Lyon
- Proceedings Conference Lyon Free of Charge by EIPC members
- New Date and Location of EIPC 50th Anniversary Conference: June 21–22, 2018, Geldern, Germany
- Smart Systems Integration 2018: Program Highlights for Visitors
- Cryptocurrency Craze Boosts Demand for Memory Chips
- DYCONEX Opts for Automated Guided Vehicles
- SCS Partners with DTI to Sponsor UK Electronics Industry at International Events
- 2018 ICT Annual Symposium, June 5, 2018, National Motor Museum
- 2018 Spring Seminar and AGM, Best Western Plus Manor Hotel, March 13, 2018
- Annual Foundation Course April 9–12; First day at Merlin PCB, Deeside, and then at Chester University
- Ventec to Showcase Thermal Management Solutions and Latest Laminate Technology at IPC APEX EXPO 2018
- Atotech to Present and Exhibit at the IPC APEX Expo 2018
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03/12/2025 | Ventec International GroupVentec International Group announce launch of VT-47LT IPC4101 / 126 Prepreg. Are Microvia Failures Plaguing Your HDI Any Layer Designs? High-density interconnect (HDI) designs are pushing the envelope - higher layer count HDI relies on complex microvia designs: skip vias, staggered microvias, and stacked microvias in sequential laminations.
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