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Mentor and Lamsim: 2018 DesignCon Best Paper Available Now
March 20, 2019 | Mentor, a Siemens businessEstimated reading time: Less than a minute
High-speed PCB designs are getting faster and faster. However, as the rate of GB/s increases, so too does the need to pay attention to material properties. Copper roughness, the area where the copper adheres to the laminate, is one of those properties. This 2018 DesignCon Best Paper award-winner describes a technique for increasing simulation accuracy through proper modeling of copper roughness.
This paper was written by Vladimir Dmitriev-Zdorov and Igor Kochikov of Mentor, a Siemens business, and Bert Simonovich of Lamsim Enterprises. To download this paper, click here.
Suggested Items
Copper Price Surge Raises Alarms for Electronics
07/15/2025 | Global Electronics Association Advocacy and Government Relations TeamThe copper market is experiencing major turbulence in the wake of U.S. President Donald Trump’s announcement of a 50% tariff on imported copper effective Aug. 1. Recent news reports, including from the New York Times, sent U.S. copper futures soaring to record highs, climbing nearly 13% in a single day as manufacturers braced for supply shocks and surging costs.
I-Connect007 Editor’s Choice: Five Must-Reads for the Week
07/11/2025 | Andy Shaughnessy, Design007 MagazineThis week, we have quite a variety of news items and articles for you. News continues to stream out of Washington, D.C., with tariffs rearing their controversial head again. Because these tariffs are targeted at overseas copper manufacturers, this news has a direct effect on our industry.I-Connect007 Editor’s Choice: Five Must-Reads for the Week
Digital Twin Concept in Copper Electroplating Process Performance
07/11/2025 | Aga Franczak, Robrecht Belis, Elsyca N.V.PCB manufacturing involves transforming a design into a physical board while meeting specific requirements. Understanding these design specifications is crucial, as they directly impact the PCB's fabrication process, performance, and yield rate. One key design specification is copper thieving—the addition of “dummy” pads across the surface that are plated along with the features designed on the outer layers. The purpose of the process is to provide a uniform distribution of copper across the outer layers to make the plating current density and plating in the holes more uniform.
Trump Copper Tariffs Spark Concern
07/10/2025 | I-Connect007 Editorial TeamPresident Donald Trump stated on July 8 that he plans to impose a 50% tariff on copper imports, sparking concern in a global industry whose output is critical to electric vehicles, military hardware, semiconductors, and a wide range of consumer goods. According to Yahoo Finance, copper futures climbed over 2% following tariff confirmation.
Happy’s Tech Talk #40: Factors in PTH Reliability—Hole Voids
07/09/2025 | Happy Holden -- Column: Happy’s Tech TalkWhen we consider via reliability, the major contributing factors are typically processing deviations. These can be subtle and not always visible. One particularly insightful column was by Mike Carano, “Causes of Plating Voids, Pre-electroless Copper,” where he outlined some of the possible causes of hole defects for both plated through-hole (PTH) and blind vias.