Elementary Mr. Watson: Running the Signal Gauntlet
The Shaughnessy Report: Winning the Signal Integrity Battle
Connect the Dots: How to Avoid Five Common Causes of Board Failure
Register Now for Mentor's PCB Systems Forum 2019 India
July 15, 2019 | Mentor, a Siemens businessEstimated reading time: 1 minute
Establishing an effective PCB systems design validation process reduces design spins and increases product quality.
Increasing performance requirements coupled with a pressure to improve product quality are driving engineering teams to consider alternatives to their current validation approach. Best-practice design processes validate the digital twin (a model of your design) early and often to minimize re-spins and actually shorten the overall design cycle. This 'shift-left' approach enables design engineers and layout designers to validate within their native environment, minimizing the bottleneck waiting for specialist reviews, and freeing the specialists to resolve the remaining critical issues. This process allows engineering teams to better cope with increasing complexity and focus their efforts on product innovation.
This event will cover research on best-practice process strategies (as well as implications of avoiding them). Case studies will show how engineering teams have deployed an ‘optimal’ automated validation process to accelerate sign-off. Analysis technologies that could be deployed within any ECAD flow will be discussed, including multi-board schematic, signal and power integrity, analog/mixed signal, thermal, vibration and manufacturability.
Solutions Covered
- Automated multi-board schematic analysis—Full inspection of all schematic nets to increase design quality and reduce re-spins
- Rule based error identification enabling checks for potential issues early and often during the layout implementation. Quickly layout and routing issues that could lead to SI, PI, EMI and other problems
- Design to manufacturing optimization with comprehensive DFM analysis, incorporated into your PCB design process
- Signal integrity analysis (pre and post layout)
- Power integrity (DC and AC) analysis for correct implementation of the power distribution network
- 3D, broadband, full-wave electromagnetic field solver for SI, and EMI
- Integrated testability analysis—Reduce overall cost of test by addressing testability considerations in schematic capture and layout
- Analog / mixed-signal simulation (inclusive of PCB material effects through automated parasitic extraction)
- Design exploration to automatically vary actual parameters in a design concept and identify high performing design option
For more information visit https://go.mentor.com/57CZf.
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