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Current IssueMechatronics
Our expert contributors discuss the advent of mechatronics in PCB design, the challenges and opportunities this creates for circuit board designers, and the benefits—to the employee and the company—of becoming a mechatronics engineer.
Creating a Culture of Collaboration
PCB designers could learn quite a bit from NASA and the private companies that develop spacecraft: Every one of these vehicles is a testament to the value of collaboration among disparate stakeholders. Without a collaborative culture, the rocket might never get off the ground.
Breaking High-speed Material Constraints
Do you need specialty materials for your high-speed designs? Maybe not. Improvements in resins mean designers of high-speed boards can sometimes use traditional laminate systems. Learn more in this issue.
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Sign Up For Mentor’s July 21 Webinar: FPGA-PCB Co-design
July 9, 2020 | Mentor, a Siemens businessEstimated reading time: 1 minute
Today’s leading-edge systems require a modern FPGA I/O optimization interface that enables you to quickly perform pin swapping and layout-based I/O optimization within the PCB design flow. Fact is, the lack of, or poor FPGA I/O optimization often leads to longer routing cycles and longer trace lengths which in turn result in the need for additional signal layers and vias which can impact signal integrity. A design tool flow with FPGA I/O Optimizer technology eliminates the barriers between FPGA and PCB designers and provides “correct-by-construction” FPGA I/O assignment allowing pin swapping and layout-based I/O optimization within the PCB process.
The ability to read in, export and synchronize FPGA designers’ HDL and constraint files ensures full consistency during the iterative concurrent design process. Incidentally, it also allows creating high pin count FPGA PCB parts ready for instantiation in minutes. Modern FPGA I/O optimization helps you not only accelerate design time-to-market, but also reduces manufacturing costs.
In this webinar by Mentor, a Siemens business, attendees will learn how modern FPGA I/O optimization can help you not only accelerate design time-to-market, but also reduce manufacturing costs.
What Attendees Will Learn
- How to create a multi-thousand pin FPGA part in minutes
- How to enable collaboration between FPGA and PCB designers
- How to optimize FPGA pin assignment in the context of the PCB layout
Who Should Attend
- Electrical engineers
- PCB designers
- Engineering managers
- Anyone interested in FPGA-PCB co-design
Date/Time
July 21, 2020
2-3 PM London Time
July 21, 2020
2-3 PM Eastern Time (US)
To register for this webinar or for more information, click here.
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