-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLearning to Speak ‘Fab’
Our expert contributors clear up many of the miscommunication problems between PCB designers and their fab and assembly stakeholders. As you will see, a little extra planning early in the design cycle can go a long way toward maintaining open lines of communication with the fab and assembly folks.
Training New Designers
Where will we find the next generation of PCB designers and design engineers? Once we locate them, how will we train and educate them? What will PCB designers of the future need to master to deal with tomorrow’s technology?
The Designer of the Future
Our expert contributors peer into their crystal balls and offer their thoughts on the designers and design engineers of tomorrow, and what their jobs will look like.
- Articles
- Columns
Search Console
- Links
- Media kit
||| MENU - design007 Magazine
Book Excerpt: Power Integrity By Example, Chapter 5
July 16, 2020 | Fadi Deek, Mentor, a Siemens BusinessEstimated reading time: 2 minutes

The following is an excerpt from The Printed Circuit Designer's Guide to... Power Integrity by Example, written by Fadi Deek of Mentor, a Siemens Business. In this free eBook, Deek addresses problematic issues within electronic transmissions, and presents a variety of simulations and analyses in every chapter.
Chapter 5: Reducing Via-to-Via Coupling Using Capacitors
The peak noise shown in Figure 4.4 from a single rising-edge simulation was around 10 mV of noise with the aggressor switching up to 800 mV. This means the percentage of noise coupled from one via is 10/800 mV = 1.25%.
Coming from one aggressor via, this does not seem like a significant amount. However, in a printed circuit board, there are hundreds or even thousands of vias. This quickly becomes an important issue if a fraction of vias switch simultaneously.
In order to reduce the crosstalk level from all vias at once, the impedance of the cavity should be reduced. If the impedance is lowered, that means the voltage noise level propagating through the cavity is also lowered, because the two are directly proportional, as described by Ohm’s law.
Figure 5.1: Impedance profile, with 2-mil cavity in blue and 30-mil cavity in red.
Two methods to reduce cavity impedance are explored. One method is to reduce the cavity thickness from 30 mils to 2 mils. As shown in a previous section, the impedance dropped and the cavity was almost transparent.
It is always important to examine the cavity impedance profile to know what coupling and noise to expect. A comparison of the impedance profile with a 2-mil cavity versus a 30-mil cavity is plotted in Figure 5.1. The decrease in the cavity impedance shifted the LESL – Ccavity parallel resonance to around 16 MHz and the impedance dropped, too.
Figure 5.2: Via-to-via coupling, with 2-mil cavity in blue and 30-mil cavity in red.
Based on this, the noise injected into the cavity should be reduced and the period of the ringing should be longer than before at 62 ns. A simulation was run to measure the crosstalk between the vias and is plotted in Figure 5.2. The peak crosstalk is now measured on the blue plot a little bit higher than 1.2 mV. This is a significant decrease with just one simple change—the noise level percentage dropped to 0.1% for the 2-mil cavity from 1.25% for the 30-mil cavity.
To download your free copy of The Printed Circuit Designer’s Guide to…Power Integrity by Example, click here.
To visit the I-Connect007 library and check out the entire lineup of free eBooks, click here.
Suggested Items
Real Time with... IPC APEX EXPO 2025: Discover Comprehensive PCB Solutions with American Standard Circuits
04/01/2025 | Real Time with...IPC APEX EXPOAnaya Vardya, CEO of American Standard Circuits, highlights the company's dedication to offering complete PCB solutions. The company provides free design packages and caters to various sectors, including military and telecommunications.
Sierra Circuits Inc. Chooses atg A9L Flying Probe Technology for High-speed Electrical Test
04/01/2025 | atg Luther & Maelzer GmbHatg Luther & Maelzer GmbH confirms delivery of high-speed bare board testing technology to PCB fabricator Sierra Circuits Inc. in Sunnyvale, CA.
New Cryostatic Systems Elevate Current Research on Qubits
03/31/2025 | Fraunhofer IAFThe Center Nanoelectronic Technologies (CNT) at Fraunhofer IPMS has recently acquired new cryostats for the research on qubits and the qualification of superconducting systems.
Real Time with... IPC APEX EXPO 2025: Schmoll America—Committed to Supporting Customers
03/31/2025 | Real Time with...IPC APEX EXPOKurt Palmer of Schmoll America and Stephan Kunz of Schmoll Maschinen GmbH had a great show, reporting solid attendance and good opportunities, as Schmoll America celebrates its first anniversary. With a booth full of equipment for attendees to see and touch, they showcased unique products like the Pico laser and X-ray machine, and discussed plans for a new facility.
HARTING 3D-Circuits Leads 3D-MID Innovation: Transforming Consumer Electronics with Advanced Technology
03/27/2025 | PRNewswireThe consumer electronics industry is experiencing a remarkable transformation, propelled by rapid technological advancements and an increasing demand for compact, efficient, and multifunctional devices. Central to this evolution is 3D-MID (Three-Dimensional Mechatronic Integrated Devices) technology, which redefines design standards and drives innovation.