Real Time with… SMTAI 2020: Technical Conference Review

Estimated reading time: 16 minutes

The rollout of 5G networks has already started worldwide. In the near future, it is expected to dramatically reshape the wireless communication implementation landscape. Nevertheless, a number of technical challenges still need to be addressed in the most recent packaging development approaches, such as the implementation of a large number of connections at high data rates exhibiting high gain to compensate for the high free space loss at millimeter-wave frequencies.

Within the European funded project SERENA, partners from academia, research, and industry are collaborating to address these topics and develop an integration platform, based on PCB embedding technology, capable of reducing size, power consumption, and design time and complexity, while at the also achieving increased performance, energy efficiency, and transmitted output power.

In particular, PCB embedding technology offers the potential to realize an integrated RF electronics module containing ICs for RF signal generation and antennas with very short interconnects in a single package, minimizing the signal path losses. In the framework of the SERENA project, new RF materials suitable for the embedding of components are applied in combination with high-gain GaN and SiGe dies for the first time to implement a scalable SiP operating at 39 GHz.

Different concepts for the realization of RF modules with embedded GaN and SiGe dies are outlined, and first demonstrators are currently being fabricated at Fraunhofer IZM to develop a process technology which allows using RF laminate and prepreg materials to embed the dies for modularization and handle non-standard die pad metallization, such as 3-micron Au pads, within the embedding process sequence.

Test structures were also fabricated for the electrical assessment of the package configuration and the applied technology tested. Specifically, package interconnects, and integrated patch antenna arrays were designed, simulated with the aid of a 3D full-wave simulator, and measured after fabrication. It was shown that the interconnects realized in the PCB embedding technology have good RF properties in terms of insertion loss and return loss and are well suited for SiP RF modules. The antennas also exhibit good radiation characteristics in terms of gain and efficiency.

Figure 16: The motivation for embedding for RF applications.

Figure 17: Chip embedding process.

The challenges of rapidly changing products and applications for electronics continually push the requirements for IC substrates and PCBs. The industry responds with technologies, such as HDI, semi-additive processing (SAP), and modified SAP (mSAP), to meet the requirements of tomorrow. These technologies help maximize PCB real-estate usage by allowing fabricators and designers to perform multilayer buildup.

During this process, multiple metallization and etching steps are required to achieve the desired designs. With an increasing number of layers, the chance for critical defects to occur increases. Hence, a great deal of attention has been paid to the Cu deposit and how it reacts to subsequent etching processes.

Higher technologies may require many etching steps. Variations in the etching rate across the surface can result in pits forming. These defects cause severe reliability issues in the final product. Fabricators are currently trying to resolve these issues by baking the plated panels for several hours, which increases the process cost and negatively affects production output.

Therefore, innovative Cu electroplating solutions are required to produce Cu deposits that etch consistently. The purpose of this study was to investigate the underlying mechanism of pitting and to develop an innovative process to reduce pit formation. The electrolytic process also needed to be robust enough to perform consistently in large scale production.

Figure 18: Etching steps can lead to V-pit formation. Pits can cause failures in finished products.Page 5 of 7

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