Elementary Mr. Watson: Navigating RF—A Glide Path Approach to Design Success
Designers Notebook: Layer Stackup Planning for RF Circuit Boards
Connect the Dots: Involving Manufacturers Earlier Prevents Downstream Issues
Just Ask Heidi: Eliminating EMC Failures
December 24, 2020 | I-Connect007 Editorial TeamEstimated reading time: 1 minute
First, we asked you to send in your questions for Happy Holden, Joe Fjelstad, Eric Camden, John Mitchell, and Tara Dunn in our “Just Ask” series. Now, it’s Heidi Barnes’s turn! Heidi is a senior signal and power integrity engineer at Keysight Technologies. She has written over 20 papers on SI and PI, and she is an active member in developing the new IEEE P370 standard involving interconnect S-parameter quality after fixture removal. Heidi has been awarded five patents and a NASA Silver Snoopy award (each Silver Snoopy pin flies on a space mission first), and she was named DesignCon's 2017 Engineer of the Year. We hope you enjoy “Just Ask Heidi.”
Q: We waste a lot of time with EMC failures. It’s constant. What are your thoughts on EMC?
A: Maybe it is too simple, but if one does a great SI design, then all the energy goes from Tx to Rx and there is no radiation. It’s the same with PI: if one does a great PI design, then all the energy goes into delivering power to the load and not feeding EMC resonances. The biggest culprit is often the layout of the return path, which is trivialized in schematics with a simple ground symbol that magically connects all grounds together. As EMC/EMI expert Dr. Bruce Archambeault is often heard saying, “Ground is a place for potatoes and carrots.”
In electronics, we have return current paths. Obviously, it is never that simple in engineering and one always needs to make trade-offs. I find that even the simplest of EM simulations can start to provide significant insights into ways of reducing potential EMC problems from resonances and crosstalk.
To submit your questions for Heidi, click here.
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