Barry Olney’s High-Speed Simulation Primer

Estimated reading time: 2 minutes

The I-Connect007 editorial team recently spoke with Barry Olney of iCD about simulation. Barry, a columnist for Design007 Magazine, explains why simulation tools can have such a steep learning curve, and why many design engineers are still not using simulation on complex high-speed designs.

Barry also highlights common mistakes that design engineers make using simulation tools, and he offers a variety of tips and techniques for anyone dealing with simulation challenges. Among them: Don’t trust reference designs and datasheets.

Andy Shaughnessy: What are some of the biggest problems in simulation? In our surveys, engineers say that they have trouble doing simulation and analysis. What is so tough about it?

Barry Olney: I think the biggest problem, Andy, is time, and that’s the same with PCB design in general. The PCB design is the last process in the design flow, and when I get a job for a board layout, it’s already behind schedule. I’ve never ever had a job where it was on schedule and everything was running smoothly. So, you’re pushed for time during the whole process, and to add simulation on top of that, that pushes it back another week or so. Management is reluctant to do it because they think, “Well, it may work and then we can get it through just a little bit behind schedule, but if we leave it another week then it delays things even further.” It seems they don’t have time to do it right the first time, but they’ve got the time for a re-spin.

A lot of engineering managers actually schedule in a re-spin because they believe they need at least two iterations before they get a working product. So, time is the biggest factor. That’s why they generally tend to skip simulation. There’s also the learning curve associated with the high-end tools that requires experience—not just with the tools, but with high-speed design rules. Sourcing IBIS models is another big issue. Maybe you can’t find the model, so you have to compromise. IC vendors are now supplying most IBIS models, but for FPGAs, in particular, if you get the default IBIS model from the vendor’s website, it has a default pin assignment, but once the EE places and routes the actual FPGA chip, you need to redefine the pin assignments for each signal.

Now, the pin assignment of the FPGA that someone designs isn’t the same as the one on the IBIS model, and that’s where it all goes haywire. You think, “That simulation is simple. You just have to import the IBIS models into the transmission line model and click Go.” That should happen, but, it doesn’t. Where you don’t have pin assignments matching, you have to manually select the required FPGA sub-models from the thousands of pins with 50 or so sub-models. And these have all got cryptic names that are different for each IC vendor. So, you actually have to find the model or driver model that matches the transmission line that you’re trying to simulate. Or maybe you cannot find the model at all. Good luck sourcing a connector model. So, again, this all takes time. It took me years to figure out how to do it properly, quickly, and efficiently.

To read this article, which appeared in the April 2021 issue of Design007 Magazine, click here.