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Beyond Design: The Impact of Filled Vias on Thermal and Signal Integrity

The growing popularity of wide bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC) has enabled components to achieve higher operating temperatures and power outputs than silicon-based technology. However, this has not eliminated the need for careful thermal management to evenly distribute the heat generated to avoid the formation of dangerous hot spots and to minimize power losses. The heat generated by integrated circuits (Figure 1) poses great challenges, especially given today’s higher speeds, smaller board surface areas, and multiple devices populated on PCBs. These demands call for solutions to effectively dissipate the heat and ensure the performance and lifetime of the electronic system product. One solution is to use copper filled vias which complement thermal management, but how do filled vias affect signal integrity?

The conventional plating process cannot close the via completely—there is always an air gap in the middle. Thicker barrel plating improves the thermal transfer and current-carrying characteristics of vias at DC and low frequencies. IPC-4761 Design Guide for Protection of Printed Board Via Structures Standard covers via fabrication and protection. There are seven categories, but just three basic types:

1. Tented via.
2. Plugged via.
3. Filled via.

All three via types can also be covered (on both sides); however, the filled via may also be capped. Capped vias are generally used for via-in-pad applications to prevent paste or resin flowing down the hole—the surface is planar and solderable. Typically, vias are plated over with electroless nickel immersion gold (ENIG). However, if via-in-pad is used, then ensure the connection to the planes uses thermal reliefs or you'll have a difficult time getting the device back up if it needs rework.

I have been tenting vias with either dry film or liquid photoimageable (LPI) solder mask for over 30 years. The basic reason is to seal the via hole for vacuum test fixtures and to prevent voids in the solder mask for silk-screening the component legend. Vias can be partially plugged with non-conductive paste but there is a chance of cracks from encapsulated gas during soldering. Or they can be filled with non-conductive or conductive materials.

Proper thermal management is necessary to keep each component within safe temperature limits. The junction temperature should never exceed the limit indicated in the manufacturer’s datasheet (generally between 125–175°C for silicon-based devices). The heat generated by each component is transferred to the outside through the package and the pins. The two main techniques used to improve PCB thermal management consist in the creation of large ground planes and in the insertion of thermal vias. Thermal vias are used to transfer heat from one layer to another. Unfortunately, FR-4 does not offer high thermal transfer.

Copper-filled thermal vias provide an efficient heat dissipation path directly incorporated into PCBs with placement directly under a surface-mounted IC (the heat source). This allows direct surface mount bonding for maximum heat transfer using surface mount copper material. Specialized materials such as Kuprion’s copper thermal via paste are capable of filling vias of at least 5 mm in diameter. When fused, the copper paste converts to solid copper without melting, which provides thermal conductivities in the range of approximately 110-180 W?m^-1?K^-1 (watts per meter-Kelvin) and up to 290 W?m^-1?K^-1 for microvias (up to 25 mil in diameter).

Engineers have debated the merits of hollow vias vs. solid vias for RF performance. There is a great temptation to believe that making the via solid will somehow reduce the equivalent inductance of the structure. However, once the skin-effect kicks-in, in the megahertz range, then the current tends to only flow in the perimeter of the barrel.

Conductive epoxy-filled is the best practice for the vias to have a finished diameter between 8–18 mil. This allows the epoxy—conductive or non-conductive—to be pushed through the hole completely, but not to run out. The associated aspect ratio is best if the depth-to-diameter is less than 10:1.

A plate-shut process provides greater reliability for microvias, as opposed to filling with non-conductive ink and then plating over. Filling vias creates a solid core. This allows for a flat surface to be plated, and keeps the solder at the assembly level from leaking through and compromising the solder joint. This provides for the most reliable finished assembly.

The following materials can be used to ensure vias are sealed when filled:

1. A special plugging resin (e.g., Taiyo THP-100 DX1 thermally curable permanent hole-filling material) is suitable for plated through-hole and via-in-pad applications.
2. Copper: Classic copper via filling methods involve using pure copper to fill the hole.
3. Silver conductive epoxy resin: This is an alternative for filling vias but is expensive and copper works more effectively (e.g., DuPont CB100 or Tatsuto AE3030 screen-printed material).

PCBs that have copper-filled vias will stand up to the conditions presented by high power, radio frequency, microwave, and LED applications. The high-power integrated circuits that run these types of PCBs use currents that a copper-filled via can withstand, but not a plated through-hole.

A complete view of the current distribution can be visualized using a 3D solver. Figures 2 and 3 present three views of the conduction current at 18 GHz on a microstrip, hollow via, and solid via using Flomerics Micro-Strips, a 3D TLM solver: a) perspective view; b) top view of strip and ground plane; and c) bottom view of top strip. The scale in all three plots is 0 to 120 nA/m.

In both the hollow and solid barrel cases, the current is clearly flowing on the near side of the via barrel. There is also a small amount of current that flows down the inside surface of the via barrel. The return current in the ground plane can also be seen in Figures 2a and 3a. We tend to forget that microstrip is a two-conductor system—the return path is just as important as the signal path. Figures 2b and 3b show a top view of the complete structure. Note the non-uniform current distribution across the width of the strip. Finally, in Figures 2c and 3c, there is a view of the bottom side of the top strip.

Comparing the last two views we note that there is more current on the bottom side than the top side of the trace. At low frequencies, the current would split more or less equally between the top and bottom surfaces of the strip. But, as frequency increases, the current distribution shifts toward the bottom side of the strip due to the proximity effect. The current distribution of the hollow and solid barrel has not changed significantly at 18 GHz, although this would be quite different at DC. The equivalent inductances for the hollow via and solid via cases are virtually identical. At 18 GHz, skin depth effects alone will force the current to the surface of the solid via.

Filled vias have little impact on signal integrity at high frequency. However, there is a definite benefit in using filled vias if thermal relief is the goal. At DC, filled vias also provide increased current capacity but at 18 GHz both filled and hollow vias perform much the same.

Key Points

• Copper-filled vias complement thermal management.
• The conventional plating process cannot close the via completely.
• Thicker barrel plating improves the thermal transfer and current-carrying characteristics of vias at DC and low frequencies.
• Thermal vias are used to transfer heat from one layer to another.
• FR-4 does not offer high thermal transfer.
• Solid vias do not reduce the equivalent inductance of the structure. The current tends to only flow in the perimeter of the barrel due to the skin effect.
• Conductive epoxy-filled is the best practice for the vias to have a finished diameter between 8–18 mil.
• Filling vias creates a solid core and allows for a flat surface to be plated. This keeps the solder at the assembly level from leaking through and compromising the solder joint.
• The equivalent inductances for the hollow via and solid via cases are virtually identical.
• At 18 GHz, skin depth effects alone will force the current to the surface of the solid via.

Resources

Beyond Design: The Proximity Effect, by Barry Olney, Design007 Magazine, March 2019.

“Microwave Circuit Modeling using Electromagnetic Field Simulation.” D. Swanson and W. Hoefer, Guide to Copper-Filled Vias, Process & Benefits. 

Copper & Epoxy Filled Vias, Cirexx International.

“High-Power Dissipation Copper Filled Thermal Vias by Kuprion,” Power Electronics News, April 23, 2021.

 This column originally appeared in the November 2021 issue of Design007 Magazine.