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Digital Transformation: Enabling a Digital Thread Across IC/Package/PCB Design

If you’ve been keeping up with the electronics trade news, you’re probably aware that there is a slow but steady growth of ICs now being implemented in 2.5D or 3D IC configurations. Over the last decade, these device configurations have been steadily growing in popularity in highest-capacity FPGAs, high-bandwidth memory devices, and processors targeting high-performance computing and datacenters. But with Apple’s recent announcement of M1 Ultra—which will power its new generation of desktop and laptop computers—the age of 3D IC is quickly coming upon us and may become the norm rather than the exception. So, it behooves us to ask: What, if any, impact will this have on PCB systems design? 

Typical 2.5D design processes design each substrate (e.g., the ICs and interposer) separately, then integrate at the end (often with derived data like spreadsheets), where errors are found, and time-consuming iterations begin. Optimized performance of 2.5D or 3D IC configurations requires a co-design methodology across the ICs and interconnecting interposer. Likewise, co-designing the PCB(s) in context with the IC package yields the same benefit. Co-design requires a digital thread across all fabrics, ensuring that all design teams are working with the same data, and enabling cross-substrate trade-offs.  

Often the bridge between chip and system PCB, IC packaging offers the best opportunity for optimizing signal performance, power delivery/integrity, and interconnect optimization. Using a multi-substrate design approach, simulation becomes an achievable reality, from the chip’s buffer block through package routing and on to system PCB implementation. Optimizing critical signals down interface paths throughout the system will result in far fewer downstream issues that will require resolution.

The traditional path to system design is to know what you need to build, to identify what must be done, and then to design to those requirements. The defense and aerospace industries have had great success enforcing this method of constrained design, especially for complex system designs where the correct-by-construction approach speeds design time, improves quality, and lowers costs by reducing design iterations.

The correct-by-construction approach forces designers to make assumptions regarding the limiting issues in the design and then to simulate these assumptions in software before building a physical prototype. Before translating a conceptual design limitation into a physical design constraint, designers must understand the source of the challenge and where to go in the design to resolve it. This requires designers and engineers to see the big picture to make good decisions.

Visualizing and comprehending the entire multi-substrate design while keeping essential and critical design requirements in mind often overwhelms the designer and design team. Typically, the task of creating a new SoC/chip, its corresponding package, and a new system board(s) involves three different engineering teams with three different perspectives. Although it can be possible to get the different design disciplines together in a coordination meeting, a successful joint plan really requires a methodology, process, and usually some technology and automation for tying these worlds together.

There are three concepts that, when added to traditionally deployed design methods, can enable the creation of an optimal system product: multi-substrate visualization, system-level cross-substrate interconnect untangling, and cross-substrate co-design. Multi-substrate visualization means not solving micro, or single substrate design issues until you can see the whole picture. Once you step back and look at the whole design, the pieces of the solution start to become clear.

When designing a new die such as a processor, the system target is an industry-standard memory chip with a fixed pin-out. Unraveling starts from the system PCB and drives toward the die, as the PCB design domain drives the optimization. If you co-design the PCB, package, and die, pre-optimization enables ideal, easy-to-implement routing. Co-design provides design flexibility in all three domains, as the design of the target PCB, package, and die pads all begin at the same time.

System-level optimization isn’t just about simplifying the life of the poor PCB engineer, who is often on the receiving end of a complex new 2.5/3D IC. A streamlined co-design methodology that seamlessly interchanges digital twins of ICs, packages and boards optimizes collaboration and minimizes rework. Attacking the full system problem at one time, rather than in discrete and serial chunks, enables performance optimization and cost reduction at each substrate level.

This column originally appeared in the May 2022 issue of Design007 Magazine. 

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