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Cadence Revolutionizes System Design with Optimality Explorer for AI-Driven Optimization of Electronic Systems
June 10, 2022 | Cadence Design Systems, Inc.Estimated reading time: 3 minutes
Cadence Design Systems, Inc. announced the Cadence® Optimality Intelligent System Explorer, which enables multi-disciplinary analysis and optimization (MDAO) realization of electronic systems. After revolutionizing simulation and delivering several products with breakthrough performance and accuracy, Cadence has focused on optimization, first introducing the disruptive Cadence Cerebrus™ Intelligent Chip Explorer, and now Optimality Explorer. Leveraging similar AI technology as used in Cadence Cerebrus to yield groundbreaking results, Optimality Explorer delivers optimized designs on average 10X faster than traditional manual methods, with up to a 100X speedup realized on some designs. Optimality Explorer further extends Cadence’s system analysis leadership by delivering to market an industry first: an AI-driven, MDAO-enabled in-design multiphysics system analysis solution.
Cadence’s Clarity™ 3D Solver for 3D electromagnetic (EM) analysis and Sigrity™ X technologies for high-speed signal integrity (SI) and power integrity (PI) analyses are the first Cadence multiphysics system analysis software products to embrace Optimality Explorer. With Optimality Explorer, Clarity and Sigrity X solvers can significantly improve designers’ productivity and efficiency by enabling design teams to explore the entire design space and quickly and efficiently converge on the optimal design.
Optimality Intelligent System Explorer delivers the following benefits:
- Design insight: Enables designers to quickly determine optimum electrical performance, avoiding suboptimal local minima and maxima, while mapping variations for additional consideration and exploration of the complete design space
- Improved productivity: Empowers design engineers and teams to efficiently achieve optimized system-level designs, improving productivity by 10X on average when compared to manual, brute-force parametric table studies, with up to a 100X speedup realized on some designs
- Easy-to-use interface: Flexible use model allows customers to activate Optimality Explorer from the Clarity and Sigrity X environments for fast invocation of MDAO
- Extensible solution: Allows customers to extend AI-driven optimization across Cadence’s multiphysics technologies to create a comprehensive computational software solution spanning simulation, optimization and signoff
“For years, optimization at the system level has been extremely inefficient based on a human-intensive workflow of design/prototype/test/refine and eventual manufacturing,” said Ben Gu, vice president of R&D for the Multiphysics System Analysis Business Unit at Cadence. “With Optimality Explorer’s MDAO capability, it’s now possible to perform system-level optimization, from the IC to the package, the PCB and the system, in a fraction of the time and with Cadence’s signature gold-standard accuracy.”
Customer Endorsements
“In a high-speed package design, it’s a cost- and performance-effective process to optimize the design before taping out. For our DDR package optimization process, Cadence’s Optimality Explorer-empowered Clarity 3D Solver enabled us to uncover the best parameter configuration, meeting our design criteria in a dramatically shorter time window, thereby speeding up our time to market while enabling us to deliver a higher performing solution,” said Alan Zhu, VP of Hardware at Ambarella.
“The Clarity 3D Solver provided unparalleled speed and capacity with proven accuracy throughout our next-generation Kunlunxin AI chip project. We utilize Clarity 3D Solver for high-speed channel modeling and optimization. Now, with Cadence’s Optimality Explorer, we reduced the amount of time we spent on optimizing transmission line performance from hours to minutes. We were able to tune the physical parameters of a high-speed differential pair routing constraint much faster than previous methodologies. The time saved can be used to optimize other parts of our design so that all critical interfaces operate at peak performance,” said Canghai Gu, Chief Chip Architect of Kunlunxin at Baidu
“MediaTek is a leader in SerDes design and technology. The Cadence Optimality Explorer and Clarity 3D Solver allowed us to realize a 75% performance improvement for our recent 112G PAM4 SerDes project. The optimum return and insertion loss, and TDR waveforms, were determined quickly and efficiently due to Cadence’s breakthrough AI-driven optimization, accelerating the design team’s productivity and ultimately the success of the final product,” said Aaron Yang and Howard Yin, Design Directors at MediaTek.
“As an early adopter of the Cadence Optimality Intelligent System Explorer, we stressed its performance on a rigid-flex PCB with multiple via structures and transmission lines. The Optimality Explorer’s AI-driven optimization allowed us to uncover novel designs and methodologies that we would not have achieved otherwise. Optimality Explorer adds intelligence to the powerful Clarity 3D Solver, letting us meet our performance target with accelerated efficiency,” said Kyle Chen, Principal Hardware Engineer at Microsoft.
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Simon Khesin - Schmoll MaschinenSuggested Items
A Designer's Focus on High Density
04/30/2026 | Marcy LaRont, I-Connect007 MagazineVern Solberg is a distinguished member of the Global Electronics Association Raymond E. Pritchard Hall of Fame and has served as chair or vice chair of many committees, developing technical standards and implementation guidelines, including the IPC-7090 series, which focuses on design for manufacturing and reliability for electronic assemblies. He’s a long-time contributor to Design007 Magazine, and he conducted a half-day tutorial at APEX EXPO 2026, where he addressed 2D, 2.5D, and 3D packaging and ultra-high density hybrid bond interconnect. I caught up with Vern at the show and asked about his pivot from addressing more standard design challenges to his focus on high-density circuits.
Zuken Launches GENESYS 2026 to Broaden Access and Improve MBSE Workflows
04/28/2026 | ZukenZuken announced GENESYS 2026, the latest version of its model-based systems engineering platform, with updates designed to improve performance, expand access to model-based information, and enhance the day-to-day modeling experience for engineering teams.
EDADOC: Building the ‘Neural Hub’ for High-Compute Chips Within a Compact Space
04/28/2026 | ECIOEvery chip to the market must pass a stringent checkpoint before shipment known as ATE testing. Serving as the physical “neural hub” that connects test equipment worth millions of dollars with the device under test, the performance of the ATE test board directly determines the accuracy, efficiency, and final yield of chip testing. Amid the rapid rise of high-compute chips, what extreme challenges is this seemingly small circuit board facing? How is EDADOC addressing industry pain points through its one-stop “design + manufacturing” model?
Cadence Reports Q1 2026 Financial Results
04/28/2026 | Cadence Design SystemsCadence had a strong start to 2026, delivering a solid Q1 with accelerating AI demand and record backlog, reflecting strong customer commitment to our AI-driven portfolio,” said Anirudh Devgan, president and chief executive officer.
Tomachie Launches AI-Powered PCB Analysis with Smart Test Point Insertion
04/28/2026 | TomachieTomachie announced its AI-Assisted PCB schematic design analysis platform, enabling engineering teams to evaluate and improve schematic quality before layout begins. Schematic errors caught after layout — or in production — cost 10 to 100 times more to fix than those caught during schematic capture.