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Elementary, Mr. Watson: Advanced Packaging Not a Passing Fad

As it is said, necessity is the mother of invention. That is precisely the situation when we are discussing the PCB design industry. We are living in what can only be described as the golden age of Electronics. The advancements and innovations are growing by leaps and bounds. Never in history has the field of electronics grown at such a fantastic rate. The advance integration packages field is one of the fastest-growing and most exciting.

In 2020 the advanced packaging market was worth $24 billion. In the future, it will be more of the same; it's estimated to have a compound annual growth rate (CAGR) of 8%. That phenomenal growth is a result of the consumers' demand. They want the latest and greatest. They are expecting something better than what came out last year, what I describe as an insatiable appetite for something bigger and better with higher speeds in a smaller package, most of all inexpensive, drives our industry. It keeps us employed. This demand is on full display when Apple puts out the latest and greatest, and folks are camped out days before waiting for the release. This trend shows no signs of slowing down. Advance packaging is getting noticed by the industry as the solution to the high demand. Government legislation with the CHIPS Act focuses on domestic semiconductor fabrication. The aim should be to increase the advanced package industry into the mainstream.

Challenges with Advance Interconnect
Ever since Jack Kilby of Texas Instruments created the first hybrid IC made of Germanium in 1958, and Robert Noyce created the first monolithic IC in 1959, the IC has generally remained the same. Except for one significant difference, reducing the size of the transistors that make up every IC. What I mean by that is when Kilby and Noyce created the first ICs, the size of the transistors was 11nm. With smaller transistors, more nodes, as they are called, are in each IC.

By 1965, Gordon Moore estimated that computers' speed and capability could expect to double every two years because of increases in the number of transistors a microchip can contain. So it was a shocking statement that Moore made when he announced that a single IC would someday hold 65,000 transistors. The size of IC nodes is now being mass-produced at 5nm, which was commercially released in the Apple Bionic Chip for the A14. The transistor count now sits at a staggering 11.8 billion, a 38.8% increase from the A13's transistor count of 8.5 billion.  

It is even going smaller to 2nm by 2024. So to give you some perspective here, that is smaller than the Human DNA and would hold over 50 billion Transistors on a chip the size of a fingernail.

But before we pop the cork on the champagne, I believe we have or are very close to reaching the limits on what is physically capable of producing chips reasonably and reliably. Simply controlling the current flow in such a small area is very difficult as things shrink. In other words, we are now getting so small that we can no longer control the electrons.

We are simply running out of room. It is strongly believed by many, including CEO Jensen Huang of Nvidia, who proudly announced in 2022 that Moore's Law was dead. I am not personally at that point yet, but I will say Moore's Law is on Life Support. Although we call it a law, it was more of an observation. Even Moore agreed. In his publication Cramming More Components onto Integrated Circuits of April 19, 1965, admits "including micro-assembly techniques for individual components, thin film structures, and semiconductor integrated circuits. Each approached evolved and rapidly and converged." And in an interview in April 2005, Gordon Moore stated that the projection could not be sustained indefinitely: "It can't continue forever. The nature of exponentials is that you push them out, and eventually disaster happens." He also noted that transistors eventually would reach the limits of miniaturization at atomic levels:

In terms of size [of transistors], you can see that we're approaching the size of atoms which is a fundamental barrier, but it'll be two or three generations before we get that far—but that's as far out as we've ever been able to see. We have another 10 to 20 years before we reach a fundamental limit. By then, they'll be able to make bigger chips and have transistor budgets in the billions.

Yet another major problem is making all the interconnects to a high-density device to where it is a functional item on a PCB design. Conventionally that is done through wire bonds, which have not scaled down at the same pace as the transistor. With 11.8 billion transistors in a single chip, that is more processing power than wires can carry. Getting signals from the Silicon out to the real world, which connects to the PCB, is a significant issue.

Frankly, we are reaching the industry limitations in more ways than one.

A Paradigm Shift of Advance Packaging  
Occasionally it's good practice to examine how we do things. With advance packaging technology (APT), it is a new paradigm shift for the entire industry. Advanced packaging promises to solve the challenges we face. The basic definition of APT is the aggregation and interconnection of components before traditional electronic packaging. Advanced packaging allows multiple devices (electrical, mechanical, or semiconductor) to be merged and packaged as a single electronic device. They are taking different circuits that were separate chips on the PCB design before and placing them all in a single chip.

Although we are not specifically talking about applications when speaking of APT, we will find that particular packaging methods are popular with various industries. For example, high-end AI products such as smartphones and graphic processing units lean more towards 2.5D technology. The industry demands target specific applications and markets with how the various individual circuits are combined with the packaging methods.

The various methods of advanced packaging are listed below.

• Wafer level packaging
• 5D and 3D
• System-in-package
• Bumping and flip-chips
• Chip scale packages
• Redistribution layers
• Embedded die substrate
• MESM and microsystem packaging

Inherent Problems With APT
The APT comes with several inherent problems. The first is power dissipation and power use, and directly connected to that is the increase and necessity of heat dissipation. Traditionally silicon generates a lot of heat and is not thermally efficient. It is now seeing a decrease in voltages but to maintain or increase the power means an increase in current. How is this power migrated through the package and the heat dissipated? Even just a single chip can have problems with power consumption and heat. Now we combine them with other items such as in a system-in-package that also holds the microprocessor, the flash, and the SRAM all in a single chip. We’ve just increased the issue exponentially.

Known Good Die (KGD)
When combining the various individual parts, especially when designing a SiP design package, It is unknown if an individual circuit works until it is in the final package configuration. Because specific devices cannot be adequately tested beforehand, The failure rate is high and is expensive with lost production time. That is an issue known to the industry as Known Good Die. How the individual dies are tested and validated must be solved. Usually, only find out about these issues until it's too late.

Cost Issues
Most integrated circuit manufacturers' equipment is not ready for the onslaught of advance packaging. The equipment for such a process is highly specialized and expensive. This specialty requirement is driving up the cost of APT devices on the market. In the future, we should expect that costs should come down.

Conclusion
Advanced packaging technologies have a bright future. The insatiable appetite that the everyday consumer is looking for and expecting from their devices is increasing, driving this new technology. A technology that is now mainstream. As we finally put to rest Moore's law and change how we look at the semiconductor industry with a new major paradigm shift. Instead of simply looking at increasing node density, we can now customize based on entire sections of circuits for a specific industry and application. It's an exciting time.

This column originally appeared in the January 2023 issue of Design007 Magazine.