What Designers Should Know About Test

Estimated reading time: 2 minutes

Bert Horner, president of The Test Connection, Inc. (TTCI) in Hunt Valley, Maryland, has been helping PCB designers address design-for-test challenges, as well as the need to consider DFT early in the design cycle. I asked him to discuss some of the DFT issues that PCB designers need to be more aware of, and what designers can do to help PCB manufacturers avoid test problems farther down the line. As Bert says, many DFT snafus could be avoided if designers had a better understanding of the actual testing process.  

Bert, what are some things that designers need to know about designing for test? 

Bert Horner: Of course, test is an integral part of the manufacturing process. Often, designers will design a board that works, but it may only work in a lab or a non-production environment. With DFT, there are really only a couple of key things that you'll need to consider. One is the controllability of parts; you want to be able to disable, control tri-state, and do certain things to have controllability of the card as you're testing areas of the circuitry. You look around at the different control ports, and if you want to utilize things like boundary scan, make sure the five key pins have some kind of access, whether it's going through a header or a bed of nails, where you can access that point to utilize the boundary scan capabilities on the board. Then you’ll have that controllability in utilizing test tools.

Also, be sure to have access to allow for enough power and ground points on the board so you have a balance and you don't have ground bounce. If you're looking at ICT, flying probe, or anything with a bed of nails, you want physical access so you don't have to have the big 0.032" points. Different probing technologies allow you to utilize smaller center-to-center spacings. You can use a through-hole device as a test point on a net; just utilize an unmasked via and call it a test via. Normally on a bed of nails, you don't want to go below 0.018" to .020" in diameter; you want to stay in 0.039", 0.050", 0.075", or 0.100" center-to-center spacing. 

When you look at testability, controllability, having enough power and ground points on the board, and then the physical access, you realize that DFT could be setting up your test strategy. I know I will be looking at these bypass caps with AOI, and AOI or testing will be looking at this, so I don’t need to have test points all over that part of that circuitry. If you’re in RF, or even just high-speed digital, you might say, “I can't have test points hanging off that because there are a whole bunch of RCLs hanging off that location.” Well, what can we test, and how do we test that high-speed portion of that board through a black box when not everything is high speed? 

To continue reading this conversation, which appeared in the January 2024 issue of Design007 Magazine, click here.