Indium’s Sze Pei Lim to Present on Semiconductor Packaging at ICEP Japan

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Indium Corporation’s Senior Global Product Manager for Semiconductor and Advanced Materials, Sze Pei Lim, is scheduled to present at the International Conference on Electronics Packaging (ICEP 2024). The presentation will take place on April 18 in Toyama, Japan, as part of the iNEMI session. During the presentation, Lim will discuss the results of a technical paper titled Low-Temperature Material Discovery and Readiness for First-Level Interconnect in Semiconductor Packaging. The full conference is being held April 17-20.

Today’s industrial needs necessitate more in-depth study into the assembly process challenges, materials properties, reliability performance, and feasibility of employing low-temperature material for first-level interconnects. Most of the current flip-chip, or first-level interconnects, use SAC alloy solder bump or SnAg alloy on Cu-pillar. With both the thinning and enlargement of die, warpage is a constant challenge in the assembly process. Lower die-attach temperatures help to minimize warpage caused by high temperatures, while temperature-sensitive substrates, die, and sensors may also require lower processing temperatures. Interconnect materials with a hierarchy of various processing temperatures are necessary to prevent remelting during subsequent reflow processes. Lastly, lower processing temperatures reduce energy consumption and minimize carbon footprint in the manufacturing process. 

“If Sn-Bi-based solder alloys are carefully designed, with optimized production processes, SAC and low-temperature solder hybrid joint systems can revolutionize thermomechanical and fatigue performance with benefits such as low-temperature reflow and better drop and thermal shock resistance to high-temperature applications,” said Lim.

As the Senior Global Product Manager for Semiconductor and Advanced Materials, Lim works closely with the R&D and manufacturing teams and collaborates with leading semiconductor companies and contract manufacturers around the world. She is a task force member of the International Electronics Manufacturing Initiative’s (iNEMI) Packaging Technology Integration Group and has co-chaired several industry projects and road mapping initiatives over the past five years. She is also a member of the executive committee of the Institute of Electrical and Electronics Engineers (IEEE) Packaging Society Malaysia Chapter. Lim is a part of the organizing committee for the International Electronics Manufacturing Technology (IEMT), and has authored several technical papers. She regularly presents at international technical conferences. Lim earned her bachelor’s degree from the National University of Singapore, where she majored in industrial chemistry with a focus on polymers. She is a Certified SMT Process Engineer and has earned her Six Sigma Green Belt.