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Designers Notebook: Impact of Advanced Semiconductor Packaging on PCB Stackup

To accommodate new generations of high I/O semiconductor packaging, printed circuit board fabrication technology has had to undergo significant changes in both the process methods and the criteria for base material selection and construction sequence (stackup). Many of the new high-function multi-core semiconductor package families require more terminals than their predecessors, requiring a significantly narrower terminal pitch. Interconnecting these very fine-pitch, high I/O semiconductors to the PCB is made possible by an intermediate element referred to as an interposer. The interposer enables the interconnect of the semiconductor package with an ultra-high-density socket (Figure 1), for example, that is configured to interface with a conventional FR-4 laminate-based, multiple layer printed circuit board.

When defining the complexity level for the circuit board, the designer will first establish a criterion for fabricating the circuit board. This will include the board outline and thickness limitation. In regard to controlling the specified circuit board thickness limit, a clear objective must be established to identify the number of circuit layers that are to be dedicated to signal routing and the number of layers reserved for power and ground distribution. Estimating the required number of signal layers will be determined by the component density and interconnect complexity. The number of power and ground layers will be determined by the number of ground terminals on the components and any requirements for multiple operating voltages.

Before beginning the circuit board design process, experienced professionals advise the designer to perform an interconnect capacity analysis. This analysis is based on the board’s usable area and terminal number for all components defined in the parts list, but it excludes the circuit conductors. To determine the basic component area, the designer must first gather mechanical outline specifications and electrical data for all active and passive component parts.

From this data, the designer can assign the associated land pattern geometries and pad stack from the pre-established CAD library. To calculate the basic area required for component placement and conductor layers needed for circuit interconnect, designers must contemplate the land pattern features for mounting the components, define “keep out zones,” establish clearances reserved for assembly process evaluation, and, when necessary, post assembly rework and repair. The final analysis will provide the designer with an estimated maximum surface area needed to complete all circuit interconnects.

Establishing Circuit Routing Criteria
Although printed circuit board fabrication process capabilities have continued to expand on a global scale, fabrication process capability from one supplier to another, however, is not likely to be equal. This is because of the continuous advancement in related chemistries, processing systems, materials, and overall process control evolution. Ensuring the success of the end-product’s functionality requires an understanding of the designated fabricator’s primary capability attributes and how design complexity will affect the printed circuit board’s producibility and cost.

Following component placement, the CAD system’s auto-router will assist the designer in determining the expected interconnect completion rate. The auto-router function can also be used to aid the designer in identifying circuit routing bottlenecks or other critical interconnect issues not identified during the initial component placement process. If the interconnect result is less than 85%, then it is a likely indication that the designer will need to make some adjustments to component placement. In regard to auto-routing for frequency management applications, CAD routing tools are very good, but conductor routing on circuit boards requiring controlled impedance or selective conductor shielding will likely require a degree of interactive manipulation by the design engineer.

When component density and interconnect complexity exceed the area defined by the PCB outline, a higher level of fabrication technology will be justified, requiring additional circuit layers and/or increased conductor interconnect density. Electrical interconnect on internal layers for the board enables significantly greater circuit routing density. The circuit path between key components can be more direct as well, providing greater circuit speed and lower resistance. To ensure the greatest interconnect efficiency, the designer should alternate the overall direction of the circuit path from one layer to another, using plated via-holes to accommodate direction change as needed. With the circuit width and space requirement already established in the CAD system, the auto-router function can quickly complete the initial interconnect process.

Three technical levels of capabilities for circuit conductor routing on the inner layers of the circuit board are presented in Table 1: standard, advanced, and capability classified as emerging technology.

The capability shown in the emerging technology column may be a standard capability for some fabricators but, for others, the process will require improvement in process control and chemistry refinement. The individual circuit board supplier’s standard level of complexity will generally represent what is recommended to achieve their highest yield and most favorable unit quality. The circuit routing complexity and copper foil thicknesses on the external surfaces of the multilayer printed circuit board fabrication may differ from those routed on the inner layers of the stackup.

The final process stage for the multiple layer circuit board is lamination of all the circuit layers, including the two external layers. Following lamination, via holes will be drilled or formed, followed by a number of plating steps to fill holes, and in some cases, build up the conductor pattern thickness. A series of imaging, plating, and chemical etching processes takes place for the two external layers. Depending on the board fabricator's capability, conductor routing on the external surfaces of the circuit board may require a slightly different requirement for conductor routing. The data furnished in Table 2 may be required by the supplier, and although it will have an impact on circuit routing density, fabrication yield may be a factor.

Stackup Planning for High Density Multilayer Circuit Boards
A PCB stackup plan must be developed to define the order, thickness, and materials used for each layer of the circuit board. The circuit layers are either dedicated to routing signal traces or to provide for power and ground distribution. The fabricators emphasize the importance of the layer stackup order and how it affects both end-product performance and functionality. Key concerns include maximizing signal integrity, impedance control, power and ground distribution, and avoiding excessive thermal concentration (hot spots).

The primary materials used for the multiple layer circuit board are the copper foil to form the interconnect, the glass-reinforced epoxy-based laminate material for the core structure, and prepreg material for bonding the layers together.

• There is a wide range of copper foil thicknesses available, but the most common PCB copper specified for multilayer PCB applications is 17.5-micron. However, when very higher circuit density is warranted, the circuit board fabricator may implement a semi-additive copper forming process that uses a much thinner (5-miron, 9-micron, or 12-micron) copper foil.
•  A glass-reinforced epoxy material developed expressly for printed circuit core has been (and will continue to be) the work-horse of interconnection technology. The materials are widely available, very versatile, and can be tailored to accommodate different product functions or applications. Although all epoxy/glass laminates have similar physical attributes, the products that adapt these materials often have very different manufacturing focus and performance requirements.
• The prepreg materials are a dielectric engineered to bond the copper foils to each other and to the copper-clad core structure of the multilayer circuit board. The thickness of the prepreg material selected for the multilayer board will vary, depending on the number of circuit layers and the maximum finished board thickness specified.

In the past, the circuit board designer did not get an opportunity to be involved with the planning of the layer stackup sequence strategy used to build the circuit board. The design tools simply didn’t have the sophistication for board layer stackup and configuration capabilities that they do today. That responsibility for stackup planning was transferred to the experts, the actual fabricator of the circuit board. Once established, the designer would then document the circuit board’s formation with the specific material set and construction.

The fabrication process for the multiple core stack examples illustrated in Figure 2a begins with hole forming and plating, imaging, and chemically etching the circuit pattern on both sides of each core section with the exception of the two outer layers of the stack. Although the holes will be formed and plated, only the inside-facing circuit pattern will be processed. Next, the core layers are assembled using the prepreg material between the opposing copper surfaces for lamination. Holes that are furnished to interface with the conductor pattern within the now laminated structure are formed, the circuit pattern imaged, followed by copper plating to build up the surface of the conductor pattern and plate the holes. After chemical etching to define the circuit pattern on the two outer layers, the boards are made ready for solder mask application and final electrical test. The process sequence for Figure 2b will be the same for the two inner core sections, but the outer circuit pattern is referred to as a cap layer that will interface with the conductor patterns on the core sections with laser-ablated and copper-plated microvias.

Today, the printed circuit board layout process is very different, as most major CAD software developers are furnishing design tools equipped with advanced PCB layer configuration features. Although these tools establish the general order of the conductive layers, the actual construction can have significant variations. The 12-layer stackup shown in Figure 3 incorporates all of the process steps noted above but it includes a center-located core section that is referred to as a floating core.

Assembly sequence:

1. The two double core sections (circuit layers 2, 3, 4, and 5 and circuit layers 8, 9, 10, and 11) are first assembled and processed separately, typical of the example shown in Figure 2b, but without the copper foil cap layers 1 and 12 on both.
2. The two multi-core sections are then assembled with the addition of single copper-clad (floating) core for layers 6 and 7 (reserved for power and ground distribution) between the two multiple layer sections.
3. The two sections and floating core are then topped off with the two copper foil cap layers (1 and 12) and made ready for lamination.
4. Following lamination, through-holes for inner layer interconnect are drilled and cap layer microvia holes for joining layers 1 and 2 and layers 11 and 12 are formed.
5. The final stages provide copper hole plating operation, final imaging on both outer surfaces, chemical etching, and solder mask application previously described.

When designing a PCB stackup, several important considerations must be made to ensure proper functionality, signal integrity, and manufacturability¹.

1. Consider factors such as signal density, power distribution, and noise isolation.
2. Allocate power and ground planes to provide a stable, low-impedance power distribution network.
3. Maximize ground plane size to reduce noise, improve signal quality, and facilitate thermal dissipation.
4. Place decoupling capacitors near power and ground plane pairs to suppress high-frequency noise and provide clean power to components.
5. Plan the arrangement of signal layers to minimize signal degradation and maintain good signal integrity.
6. Proper layer ordering, impedance control, and controlled dielectric constants are crucial for managing signal integrity issues such as crosstalk, signal reflections, and impedance mismatches.
7. Minimize EMI through careful placement of signal and power planes, using shielding layers if necessary, and use proper grounding techniques.
8. Determine the order of signal layers to minimize crosstalk and ensure efficient routing.
9. Grouping high-speed signal layers and separating them from low-speed layers can help manage signal integrity.
10. Design the stackup with controlled impedance for critical high-speed signals.
11. This involves calculating and controlling the trace widths, dielectric thickness, and layer separation to achieve the desired impedance values.
12. Use thermal vias and distribute thermal planes to manage heat dissipation.
13. Place components with high heat production away from more sensitive components.
14. Note the capabilities and limitations of your PCB manufacturer (minimum track width and spacing, minimum drill size, and material availability).
15. Select laminate materials based on electrical performance, thermal properties, and cost.
16. Different materials have different dielectric constants, loss tangent values, and thermal conductivities that can affect the overall performance of the PCB.

Note: PCB stackup methods and design guidelines will vary somewhat from one supplier to another, depending on the project's specific requirements, such as the frequency of operation. The board fabricator selected or qualified by your company may recommend a stackup sequence different from those shown here, one that the matches their unique process procedures, environmental conditions, and industry standards.

Before investing a lot of time in the design phase of the product, make an effort to consult with the potential circuit board fabricator to review the construction options most suitable for the application. For example, when the external surfaces of the board require a greater level of conductor routing density for the high I/O very fine-pitch semiconductor interconnect, the supplier may recommend implementing the sequential build-up (SBU) process. This process enables up to three additional conductor layers to be incorporated on the external surfaces of the board but the sequential build-up process will have its own unique set of design rules.

References

1. PCB Stackup Design Guidelines, Cadence Design Systems.

 This column originally appeared in the December 2024 issue of Design007 Magazine.