Estimated reading time: 8 minutes

Designers Notebook: Heterogeneous Interposer Design Challenge, Part 1

The development of monolithic (system-on-chip) ICs revolutionized the electronics industry, enabling the creation of heterogeneous products by integrating multiple active elements within the same silicon base, which includes a central processing unit (CPU), memory functions, sensors, and communication tasks.

The benefit of integrating these functions onto a common platform is improved performance while significantly reducing the overall size and weight of the electronic product (when compared to interconnecting individually packaged IC elements). As semiconductor fabrication technology advanced, developers began to implement single semiconductor platforms with multiple CPU functions. 

The first multicore CPU was invented by Kunle Olukotun, a professor of electrical engineering at Stanford University. Domestically, multicore semiconductors became available in the market in 2005 from both Advanced Micro Devices and Intel Corporation.

The electronics industry has experienced a resurgence in semiconductor package technology. This is because an increasing number of innovative package assembly methods have evolved to further enable the industry to maximize its products’ functionality.

Traditional monolithic integration developed for the less complex applications will likely continue, but the need for multicore functionality (multiple processor units to perform distinct tasks simultaneously) arises to furnish faster processing speed and increased performance while consuming less power.

Developing a multicore semiconductor die that incorporates all the peripheral supporting functions on a single die platform is time-consuming, the semiconductor size becomes excessive, and fabrication yields are often below target. For example, although the CPU portion of the semiconductor may be perfect, if one or more of the supporting functions fails, the entire processor must be discarded. Companies soon realized that to minimize time-to-market and moderate development costs, they needed to adopt an alternative package assembly method.

Before the microprocessor, the electronics industry developed system-level products using individually packaged semiconductors and passive components using a ceramic or epoxy-glass substrate for interconnect: a multichip module (MCM). Although the original MCM soon lost favor, the concept has been resurrected using uncased (bare) die elements instead of the bulky, molded plastic encasements.

To prepare the individual silicon die elements for system-level packaging, the terminal features for interconnect are in a row and column arrangement resembling a traditional wafer-level BGA, but on a much smaller scale. This generation of components is referred to as a chiplet, defined as an integrated circuit block specifically designed to work with other similar chiplets. 

The term “chiplet” was originally coined by researchers and scientists at the University of Michigan as they began investigating ways to improve computer chip design, efficiency, and functionality. The implementation of technology has rapidly evolved over the past few years, and many experts believe it will begin to replace traditional chipsets in consumer devices due to their small size and versatility. The typical component arrangement is the central placement of the CPU die(s) on an interposer and the chiplet die units arranged closely together, placed in close proximity to the CPU (Figure 1).

Interposer Development
Developers have concluded that by clustering and interconnecting two or more silicon-based CPU die and associated small outline chiplet die in close proximity to one another, the interconnect distances can be minimized and power and ground distribution optimized. Interposers are defined as a passive serving as a mechanical and electrical interface between two or more silicon die elements, enabling communication and interconnection between component parts. An interposer usually has multiple circuit layers and may be constructed using various materials, including silicon, ceramic, or organic base materials. 

In preparation for developing the interposer for accommodating multiple CPU dies and their supporting chiplet semiconductor elements, the designer must consider the existing infrastructure’s ability to support the interconnect complexity of the product. Commonly referred to as 2.5D technology, the interposer serves as a solid base for placing and interconnecting multiple chiplet die elements. With the majority of the interface between the chiplet components and processor, the interconnect between the interposer base and host circuit board or package substrate is minimal.

Standards for Implementing Chiplet Die Elements
To advance chiplet technology, reinforce the manufacturing infrastructure, and enable greater acceptance throughout the semiconductor packaging industry, some degree of standardization is warranted. Recognizing current and future potential for the wide-scale adoption of the chiplet concept, several industry leaders have moved forward in furnishing specifications and guidelines to assist potential users in embracing the technology. 

UCIe Consortium (Universal Chiplet Internet Express) has developed an open specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.

UCIe Board members include Alibaba, AMD, Arm, Advanced Semiconductor Engineering, Inc. (ASE), Google Cloud, Intel Corporation, Meta, Microsoft, NVIDIA, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing Company (TSMC).

Member companies of the consortium have already established a robust global ecosystem in support of chiplet design. They have all agreed to endorsing an open industry standard and promoting further development of the technology.  

Also active in the technology is CXL (Compute Express Link), an industry-supported Cache-Coherent Interconnect for processors, memory expansion, and accelerators. CXL technology maintains memory coherency between the CPU’s memory space and memory on attached devices, allowing for resource sharing for higher performance, reduced software stack complexity, and lower overall system costs.

Users can simply focus on their target workloads, rather than managing redundant memory in their accelerators. The organization is also a proponent of an industry open standard interface for high-speed communications, vital for the support of emerging applications such as artificial intelligence and machine learning.

Joint Electron Device Engineering Council (JEDEC) 
JC-11 is a semiconductor industry consortium responsible for the creation and update of the registered and standard package outlines. Subcommittees generate design guidelines and standardized measuring methods for the mechanical features of microelectronic semiconductor device packages. 

Note: While the Electronic Industry Association (EIA) has established passive device outline standards, the semiconductor component package outline standards are prepared by member companies of the U.S.-based JEDEC and members of the Japan Electronics and Information Technology Industries Association (JEITA).

Status of JEDEC Standards for Chiplet Semiconductors
Chiplets are defined as segmented semiconductor elements serving a specific function and furnished as individual units. These individual functional elements are then mounted onto substrate (typically silicon or glass) to form a single, multiple-die, system-level package typical of that exhibited in Figure 2.

JEDEC member companies that choose to register their chiplet component family outlines have released several general use chiplet components. By establishing the ground rules for the package outline, it enables companies with similar or competing products an opportunity to offer package developer companies an alternative source of supply. JEDEC-registered outline documents establish the control dimensions: overall component outline, thickness range, terminal pattern, terminal type, size, and pitch. An array-configured component package family, MO-365, for example, was recently published with a terminal pitch of 0.35 mm with alternative solder ball diameters of 0.10 mm to 0.14 mm. 

Several chiplet package families have evolved with terminals furnished in an array pattern; most common is the ball grid array but some are available as a land grid array terminal pattern. While the terminal pitch (center-to-center) for the fine-pitch and wafer-level semiconductor package families ranges from 1.0 mm down to 0.40 mm, the spacing between terminals on the chiplet die families are smaller and much closer to one another. Two uncased, very fine pitch package outline documents were recently released by JEDEC JC-11 to accommodate a family of 3D stacked memory:

• MO-362B, Silicon Bottom Grid Array Column, 35-micron x 55-micron pitch
• MO-349B, Silicon Bottom Grid Array Column, 48-micron x 35-micron pitch 

Because the array pitch is so small, they will be furnished with micro-pillar terminals or simply flat lands for hybrid interconnect. (Hybrid bonding is an emerging ultra-fine pitch interconnect joining technology for multi-chip/multi-stack high-performance chiplet systems.)

When device manufacturers design their own proprietary heterogeneous products, they have control over the location of the I/O terminals and define the way the interconnect is routed between devices. Standardization of interfaces will be instrumental in adoption of these building blocks and the success of this approach to build new products. In the case where chiplet-configured devices are furnished by multiple suppliers, the user must consider that the interface and I/O location between suppliers may not always be optimized for power or noise. 

Supply Chain for Chiplet Devices
Amkor Technology, a leading provider of semiconductor packaging and test services in Tempe, Arizona, published a paper addressing the enabling of the chiplet supply chain. They acknowledge that chiplet-based architectures are not new but different, and furthermore, not all suppliers’ capabilities have been tested. Most of the solutions to date have been implemented by integrated device manufacturers (IDMs). The UCIe Consortium’s standard is a step in the right direction, putting all the requirements for chiplets in one place. That way, different suppliers entering this market have a clear idea of what to expect.

Circuits within the chiplet category will fall into three primary groups:

• Logic: Handles data, math, and decision-making
• Memory: Usually SRAM, which stores data for the logic
• Analog: Managing signals between the chip and other devices

While trends in logic semiconductor fabrication have become more efficient, the die outline may continue to shrink with each generation. On the other hand, analog semiconductor elements barely change and SRAM die have already reached their size limits as well.  

In part two of the Heterogeneous Interposer Design Challenge series, we will review current solutions and design guidelines for preparing the interposer platform for interconnecting processor die and related chiplet components.

Appearances
Vern Solberg will be conducting a half-day tutorial on “PCB Design Engineers Introduction to High Density Semiconductor Package Technologies” at APEX EXPO on Thursday, March 19, where he will address “2D, 2.5D, and 3D System-in-Packaging and Ultra High-Density Hybrid Bond Interconnect.”