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Designers Notebook: Heterogeneous Interposer Design Challenge, Part 3

Editor’s note: Part 3 of the Heterogeneous Interposer Design Challenge series highlights alternative chiplet terminal design, pattern variations, and advanced ultra-high-density hybrid joining methodologies.

In just about any industry, time-to-market will establish the difference between the leaders and followers. Any new electronic product introduced into the market must meet or exceed stated performance criteria and provide reliable service to the end user experience.

The original single-core monolithic system-on-chip developed for the earlier, less complex applications has long been superseded by the more sophisticated multiple-core variations. Furthermore, developers have separated the less complex functional elements of the system from the core functions, into individual chiplet units, resulting in improved overall product yields. Chiplet packaging has become an integral part of a processing module that makes up a larger, system-level integrated circuit.

A chiplet is an integrated circuit block specifically designed to work with other related chiplets to meet the system-level package criteria. The chiplet concept, typical of that shown in Figure 1, is not only economical, but it also accommodates unlimited design flexibility, significantly reducing system package development time.

The basic idea is that modular chips, or chiplets, can be assembled in a package and connected using a die-to-die interconnect of various functions from multiple sources in a single package outline without impacting the underlying structures. Currently, most chiplet package development is led by the semiconductor sector; however, there is a significant surge in independent startups entering the field. For those outside the tent, access to the wide range of general-purpose semiconductors in a chiplet configuration has not been as available as the packaged semiconductors. But it's early, and as soon as the industry establishes uniform standards for common-use chiplet families, chip manufacturers will begin building the supply chain.

Key issues for package developers and the circuit design specialist responsible for interposer and package substrate preparation are the standards, and whether there will be multiple sources for the primary functional semiconductor building blocks needed to economically create a system-level product. Sure, some of the products are available in a chip-scale or flip-chip configuration, but their outline dimensions and terminal pitch are compatible with the projected needs of the system-level package developer. The factors furnished in Table 1, for example, are projected requirements for chiplet-configured semiconductor elements in current and future applications.

Table 1: Projected chiplet terminal-to-land diameter

Although the chiplet-configured semiconductor may be unfamiliar to the design engineer developing the traditional circuit board-based product, the technology has been implemented by over 130 semiconductor companies, including Alibaba, Advanced Micro Devices, arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung, and TSMC in Taiwan. Together, they have established the Universal Chiplet Interconnect Express (UCIe) standard.

Multiple Die Interposer Planning
Developing the high-density interposer using chiplet technology can significantly enhance product performance by enabling much shorter circuit interconnects for critical signal paths. A typical 2.5D system-in-package (SiP) application will require interconnecting two or more uncased chiplet die elements within a single package outline, typical of that illustrated in Figure 2.

Design Strategy for the 2.5D Interposer
A typical 2.5D interposer application may support the interconnect of one or more very-high-terminal-density semiconductor or multiple, related die elements. While the upper surface of the 2.5D interposer accommodates most semiconductor redistribution and the die-to-die interface, the primary I/O channels and power and ground terminals are located on the bottom surface of the interposer.

Limiting the semiconductor package size is a challenge, especially for portable and hand-held electronic applications. Another factor is the quantity, size, and pitch of the interface terminals. The base structure (interposer material) selected must also be mechanically stable and physically strong enough to withstand elevated process temperatures experienced throughout the entire package assembly process. Base material and process attributes for the three preferred interposer variations are outlined in Table 2.

Table 2: Material and process attributes for organic, silicon, and glass interposers

Although the overall circuit density potential of the 2.5D interposer is considerably greater than that of mainstream HDI circuit boards, commercial CAD tools are available to accommodate most very-high-density (VHD) interposer development.

Package assembly process methodologies can vary a great deal, but several key issues will need to be resolved prior to beginning interposer design:

• Selection of suitable semiconductors for multiple chiplet die packaging
• Establishing sources for semiconductor wafers or glass-based panels
• Specifying the environmental operating conditions
• Defining package design constraints and process protocols
• Stipulating electrical test method and post assembly inspection criteria

D2D and D2W (interposer) Joining Methods
A goal for a growing segment of the industry is to vertically stack memory die elements. Such stacking allows for dramatically higher levels of integration for commercial and consumer electronics applications. The following will outline two joining methodologies for silicon-to-silicon and silicon-to-silicon wafer or glass-base panel interposers:

• Reflow solder
• Hybrid bonding

The interposer assembly sequence begins with placing the chiplet die elements face-down onto the interposer panel’s upper surface. The electrical interface between the die and interposer may use a tacky-flux dip-and-place process and a reflow-solder process to complete the joining of the die elements to the silicon-based interposer surface. Following the die-joining process, a non-conductive polymer under-fill material is commonly applied to provide physical reinforcement.

Reflow solder processing uses a high-temperature tin alloy-based solder composition that is plated or deposited onto the copper terminal surfaces. Flux is applied to opposing surfaces, and die elements are aligned and sequentially stacked onto each other. Reflow solder processing completes the joining process, followed by flux residue removal and polymer underfill. Hybrid bonding, on the other hand, is a solderless joining technology that differs a great deal from the solder joining methods (Figure 3).

Hybrid-bond interconnect is described as a heterogeneous or homogeneous direct-bond interconnect technology that enables vertical joining of semiconductor die-on-die, die-on-wafer, and even wafer-on-wafer without the use of solder or other additive conductive materials between the attached die surfaces. This technology is increasingly being utilized for vertically joining a wide range of semiconductor devices, such as sensors, memory, and logic die elements.

The primary advantage of hybrid-bond processing is the reduction of terminal pitch and spacing, enabling faster transmission speeds and lower power consumption. The following will compare two successful hybrid joining process variations: fusion bond and oxide bond.

Fusion-Bond (Thermo-compression Bonding)
The fusion-bond joining process is a two-stage procedure that begins with precise alignment and pre-bonding of the die elements and the interposer surface at room temperature. In preparation for joining silicon die elements, or the die directly onto the wafer platforms, a layer of tin (Sn) is first applied to the exposed copper terminal features. Following pre-bond, the die elements are exposed to an annealing process that includes high temperature and pressure. When the stacked die or wafers are heated to approximately 400ºC, the tin alloy completely diffuses into the opposing copper land features to form a stable Cu-Sn-Cu (Cu3Sn) intermetallic at the land-to-land interface. The cross-section view and SEM image of the resulting bond is furnished in Figure 4.

Oxide-Bonding and Direct Bonding Interconnects (DBI)
In preparation, all surfaces to be joined are planarized and processed by chemical mechanical polishing (CMP). During the process, the copper bond lands are slightly recessed below the surrounding oxide dielectric surface. When the two polished surfaces are brought together (at room temperature), an oxide-oxide bond is formed. Then, the opposing metal terminal surfaces (Cu-Cu bond) interconnects are formed through a batch annealing sequence at 150ºC to 300ºC. During the annealing process, the Cu-Cu connections overcome the recess resulting from the CTE mismatch between the metal and the oxide, as illustrated in Figure 5.

• Align die to terminal pattern on wafer and place die onto wafer surface.
• After die placement, there is a spontaneous bond between oxide layers.
• Cu-Cu interconnect forms at elevated temperature (without external pressure).

Interdiffusion of the Cu pads requires time at temperature to complete the metallurgical bond. Since the initial oxide bonding also takes place at room temperature, Cu oxidation during bonding is minimized. The post-process example furnished in Figure 6 illustrates the two joined opposing terminals.

Note: Adeia has demonstrated D2W hybrid bonding at a 10-μm pitch with electrical test yield up to 92%. It has also demonstrated a process for cleaning and activating die mounts onto dicing tape in a dicing frame. Pick-and-place will then take place directly from the dicing frame at a demonstrated throughput of 1,636 die per hour with a single head bonder. The DBI technology can achieve one million interconnects per mm² vertically at a pitch of 1 μm.

This column will appear in the March 2026 issue of I-Connect007 Magazine.