ACCM Unveils Negative and Near-zero CTE Materials for Large-Format AI Chips

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Advanced Chip and Circuit Materials, Inc. (ACCM) has launched two new materials: Celeritas HM50, with a negative coefficient of thermal expansion (CTE) of -8 ppm/°C to offset the positive CTE and expansion of copper with temperature on circuit boards, and Celeritas HM001, with near-zero CTE and the low-loss performance needed for high-speed signal layers to 224 Gb/s and faster in artificial intelligence (AI) circuits.

Scaling of large-scale chips for AI is limited by the mismatch in CTE of circuit boards and the devices mounted on them. Manufacturing processes, including solder reflow, subject circuit assemblies to significant thermal excursions. Silicon, with a CTE of approximately 2.5–2.6 ppm/°C, must be assembled onto PCBs and substrates whose copper layers expand at approximately 17.6 ppm/°C – these copper layers dominate standard PCBs, with overall CTEs in the 17 to 19 ppm/°C range. Assembling large-format AI accelerator packages across this CTE gap produces reflow warpage, package bow, and solder fatigue failures, setting hard limits on how large, how dense, and how powerful an AI chip package can be built. HM50 and HM001 have been developed to address these thermomechanical mismatch problems at their root, enabling AI devices to perform reliably in large-format designs and expanding the architectural design space available to chip and package engineers beyond what has been achievable with conventional materials.

Celeritas HM50, with a negative CTE of −8 ppm/°C, enables circuit-board designers and manufacturers to reduce the effective CTE of a PCB stackup by counteracting the high CTE contributed by copper layers. By lowering the effective board CTE, warpage and package bow are significantly reduced and designs that formerly failed solder fatigue qualification can exceed it by orders of magnitude. Finite element analysis on a representative large-format AI accelerator platform demonstrates a 64% reduction in board warpage, an 81% reduction in package bow, and more than 100× improvement in solder fatigue life versus a standard PCB. A Tier 6 material in terms of loss, it exhibits a typical dielectric constant (Dk) of 3.55 and dissipation factor (Df) of 0.0055, both stable across frequency. Celeritas HM001 is a near-zero CTE, Tier 9 dielectric material with Dk of typically 2.90 and Df of 0.001, both stable across wide frequency and temperature ranges. It meets demanding signal-integrity (SI) requirements in high-speed circuits operating at as high as 224 Gb/s and beyond.

Keshav Amla, COO of ACCM, explains the significance of the two new materials for the growing number of AI designs in large scale form factors: “Rather than incrementally tuning stackups, we are applying a breakthrough materials innovation to remove a fundamental limitation that has constrained system scaling. Even with heavy copper designs, you could tune a board down to 12, 10, 8 ppm/°C or lower. And where next-generation data rates demand extreme loss performance, HM001 replaces those layers with a Tier 9 loss material that has a near-zero CTE. Together, HM50 and HM001 give designers headroom they simply have not had before.” Both materials are commercially available.