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Effects of DC Bias on Ceramic Capacitors

The density of multilayer ceramic capacitors (MLCC) has increased tremendously over the years. While 15 years ago a state-of-the-art X5R 10V 0402 (EIA) size capacitor might have had a maximum capacitance of 0.1 uF, today the same size capacitor may be available with 10 uF capacitance. This huge increase in density unfortunately comes with a very ugly downside: the capacitance is now very sensitive to DC and AC bias across the part.

MLCCs are manufactured with different types of ceramics. With a given case size, dielectric thickness and plate count, the capacitance is proportional to the dielectric constant of the ceramic: the higher the dielectric constant, the more capacitance we get from the same structure. For low-loss, high-performance RF and microwave applications, Class 1 materials are used. These provide very good and stable electrical characteristics, practically zero bias and temperature dependence, but their relative dielectric constant is below 100 and hence capacitance density is low. In a 0402-size package we may get 1000 pF with 50V rating. If we need more capacitance in a small package, we have to select Class 2 (or Class 3) ceramics, which are ferroelectric materials with a dielectric constant in the 200 to 14000 range.

A typical two-terminal MLCC internal geometry is shown in Figure 1. The two vertical metal terminals connect every other horizontal plate, creating a number of parallel-connected parallel-plate capacitor segments. The stack of capacitor plates fills the H total capacitor body height with an effective height of H_e. The non-connected capacitor plates should not come out to the sidewall of the capacitor body, they are pulled back to create a small G gap. 

To read the rest of this column from the February 2015 issue of The PCB Design Magazine, click here.