Reliability Study of Bottom Terminated Components (Part 2)

Estimated reading time: 5 minutes

All the parts from the package were constructed with the primary blocks available in the simulator; with properties like geometry, material type, thermal conductivity and power dissipation assigned to each part and joined all together as shown in Figure 5 and Figure 6.

Figure 5: Model Blocks

Figure 6: Device Model Assembled

Model Validation

The model validation was done comparing the thermal behavior of the model against the information provided by the supplier, with the data recorded in Table 1.

Table 1: Thermal Results from Model and Device Supplier Data

The analysis involved power dissipation at different currents resulting in a correlation index of 99% as shown in Figure 7.

Figure 7: Temperature Behavior from Model versus Device Supplier Data

Evaluation of Voiding Scenarios

With a good model that closely matches the results from the supplier data, the next step is to evaluate the voiding scenarios from 0% voids up to 98% voids and measure the temperature at the surface of the device at power dissipation from 0.5W up to 3.5W. The results are plotted in Figure 8. These results revealed that the voiding percentage has minimal impact on the temperature reached by the product.

Figure 8: Solder Voiding Impact on the Device Temperature at Different Power Dissipation

Figure 9 shows the results from the simulator in the scenario of 75% voids and 3.5W. The maximum temperature reading at the surface of the device was around 92°C. The internal semiconductor dies showed a maximum temperature of 95.4°C for Synchronous FET and 91.9°C for the control FET. The control IC reported 84.3°C. Despite the solder voiding percentage in the thermal pad being 75%, the device was dissipating 3.5W, with the semiconductor die temperatures well within the specification for this device.

Figure 9: Simulator Results for a Scenario of 75% Voids and 3.5W

Thermal Study Summary

With the aid of the thermal simulator it was possible to create and analyze solder voiding conditions in a BTC package that is difficult to do experimentally. The data indicates that the voiding in the solder joint does not significantly impact the temperature increase of the device because the rest of the elements in the package also help to conduct the heat generated. From the information collected it is possible to state that up to 50% of solder voiding in a thermal pad is acceptable for devices with power dissipation below 3W.

Conclusions

The study showed that voids did not initiate cracks in the solder joint of BTC components during thermal cycle testing from 0ºC to 100ºC. The data did not show that voids facilitate solder joint failure. Solder joints of small signal pins typically had more severe cracks and would fail first. Thermal pads usually had more voiding, but lesser cracks were observed after 3000 thermal cycles. The thermal modeling study indicated that voiding did not significantly impact the temperature increase of the device with power dissipation of about 3Watts. Further analysis would be done evaluating the thermal behavior of other BTC configurations and trying to validate with known performance of real components.

Acknowledgements

The authors would like to thank Raymond Tran, Quang Phung and the company Milpitas PIC Team for their help in the assembly. Special thanks to Manuel Haro and Jorge Alberto Aguilar for their help in the reliability study. Also thanks to Jorge Alberto Aguilar, Tu Tran and Teresita Villavert for the failure analysis and cross sectional images.

References

1. Jennifer Nguyen, David Geiger and Dongkai Shangguan, Ph. D, “Assembly Challenges of Bottom Terminated Components,” Proceeding of APEX2012, San Diego, CA, 2012.

2. Jennifer Nguyen, David Geiger and Murad Kurwa “Voiding Mitigation of Bottom Terminated Components,” Proceeding of SMTAI’13, 2013.

3. IPC-7093 standard, “Design and Assembly Process Implementation for Bottom Termination SMT Components,” March 2011.

4. Z. Feng, Ph.D., H. Le, R. Chung, R. Tran, S. Johal, and M. Kurwa, “How To Resolve Defects Related to Pad Design With the Aid of Non-Destructive and Destructive Methods”, Proceeding of SMTAI’13, 2009.

If you missed Part 1, click here.

Editor's Note: This paper has been published in the technical proceedings of IPC APEX EXPO.

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