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Overview Miniaturization on Large Form Factor PCBA
February 24, 2016 | D. Geiger, A. Mohammed, M. Kurwa, AEG, Flextronics International Inc.Estimated reading time: 10 minutes
Summary
There are many techniques that have been used in consumer type of products for miniaturization. These are now migrating into infrastructure and industrial products as increasing functional density is still a driving factor in the design of products. Miniaturization in component size, finer pitches, stacked packages, and closer component spacing is capable of being used as long as the challenges are understood and can be addressed for a particular project. The trend will continue to create more density on the PCBA and further desire to utilize miniaturization technologies. Another key are not covered in this paper would be test and inspection technologies.
References
1. Geiger, D.A., Sjoberg, J., Wong, P., and Shangguan D., "Study of Assembly Processes for Solder Flip Chips on FR-4 Substrates,” Proceedings of APEX 2003, Anaheim, CA, March 2003.
2. David Geiger, Pamela Chang, Alington Lewis, Charles Ward, Sammy Yi, Minna Arra., "Investigation of anisotropic conductive adhesive interconnect assembly process onto and organic substrate".
3. D.Shangguan, Packaging & Board Assembly Technology Trend and Impact on the Supply Chain. Keynote paper in proceedings of the sixth IEEECPMT Conference on High Density Microsystems Design and Packaging and Component Failure Analysis (HDP’04), Shanghai, China, June 2004, pp 14-17.
4. M. Arra, D. Geiger, D. Shangguan and J. Sjoberg. A Study of SMT Assembly Processes for Fine Pitch CSP Packages. Soldering & Surface Mount Technology, vol.16(3), 2004, pp.16-21.
5. Geiger D.A., Sjoberg J., Wong P., and Shangguan D., "Study of Assembly Processes for Flip Chips on Substrates,” Advanced Packaging, Nov. 2003.
6. Geiger D.A., Sjoberg J., Shangguan D., and Castello T., "Lead-Free Solder Flip Chips on FR-4 Substrates with Different PCB Surface Finishes, Underfills and Fluxes," Proceedings of Semicon West 2004, San Jose, CA.
7. Geiger D.A., Sjoberg J., Shangguan D., and Castello T., "Package on Package (PoP) Process Development and Reliability Evaluation” Proceedings of Pan Pacific 2007.
8. Geiger D.A., Sjoberg J., Lee. J., and Aranda. R., "0.3mm pitch CSP process development and PCB design” Proceedings of SMTAI 2011, Fort Worth, Texas.
Editor's Note: This paper has been published in the technical proceedings of IPC APEX EXPO.
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