Happy’s Essential Skills: Design for Manufacturing and Assembly, Part 2

Estimated reading time: 9 minutes

Predicting density and selecting design rules is one of the primary planning activity for layout. The actual layout of a PWB is not covered in these columns. The selection of design rules not only affects circuit routing but profoundly affects fabrication, assembly and test.

Balancing the Density Equation

What with the need for more parts on an assembly, or the trend to make things smaller to be portable or for faster speeds, the design process is a challenging one. The process is one of “balancing the density equation” with considerations for certain boundary conditions like electrical and thermal performance. Unfortunately, many designers do not realize that there is a mathematical process to determine the routing rules of a printed circuit.  Let me briefly explain: The density equation, as seen in Figure 11, has two parts, the left side, which is the Component Wiring Demand, and the right side, which is the Substrate Wiring Capability (equation 2).

            Component PWB Wiring Demand  <  PWBs Design Rules & Construction Wiring Capabilities       Eq. 2

Where:

          PWB Wiring Demand = total connection length required to connect all the parts in a circuit.

          PWB Wiring Capability = substrate wiring length available to connect all the components.

Four conditions can exist between wiring demand and substrate capability:

1. Wiring Demand > Substrate Capability: If the substrate capacity is not equal to the demand the design can never be finished. There is either not enough room for traces or vias. To correct this, either the substrate has to be bigger or components have to be removed.
2. Wiring Demand = Substrate Capability: While optimum, there is no room for variability and to complete the design will take an unacceptable amount of time.
3. Wiring Demand < Substrate Capability: This is the condition to shoot for. There should be enough extra capacity to complete the design on time and with only a minimum of overspecification and costs.
4. Wiring Demand << Substrate Capability: This is the condition that usually prevails. By PC layout, the schedule is tight and timing is all-important. Many choose tighter traces or extra layers to help shorten the layout time. The impact of this is to increase the manufacturing costs 15−50% higher than is necessary. This is sometimes called the “sandbag approach.” It is unfortunate, since the models above would help to create a more planned environment.     

Figure 11: “Balancing the Density Equation” to achieve an optimal layout.

Wiring Demand (Wd)^[4]

Wiring demand is the total connection length (in inches) required to connect all the parts in a circuit. When the design specifies an assembly size (in square inches), then the wiring density in inches per square inch or cm per square cm. is created. Models early in the design planning process can estimate the wiring demand. Three cases can control the maximum wiring demand:

1. The wiring required to break out from a component like a flip chip or chip scale package
2. The wiring created by two or more components tightly linked, say a CPU and cache or a DSP and its I/O control
3. The wiring demanded by all integrated circuits and discreets collectively.

There are models available to calculate the component wiring demand for all three cases. Since it is not always easy to know which case controls a particular design, it is usually to calculate all three cases to see which one is the most demanding and thus controls the layout.

Wiring demand is defined as:

                        Wd = Wc x e   (in cm/square cm or in./square in.)                       Eq. 3^[4]

            Where: Wd = Wiring Demand

                                    Wc = Wiring Capacity

                                    e = PWB Layout Efficiency

Wiring Capacity (Wc)

Substrate wiring capacity is the wiring length available to connect all the components. It is determined by two factors:

1. Design Rules—the traces, spaces and via lands, keepouts, etc., that make up the surfaces/layers of the substrate
2. Structure—The number of signal layers and the combination of through, and buried vias that permit interconnection between layers and the complex blind, stacked and variable depth vias available in HDI technologies.

These two factors determine the maximum wiring available on the substrate. The maximum wiring times the layout efficiency is what is available to meet the wiring demand. The data is straightforward except for layout efficiency. Layout efficiency expresses what percentage of wiring capacity can be used in the design. The equation for wiring capacity for each signal layer is below. The total substrate capacity is the sum of all the signal layers:                 

     Defined as:       Wc = T x L / G   (in cm/square cm or in./square in.)        Eq. 4 ^[4]

  Where: T = number of traces per wiring channel or distance between two via pads

              L = number of signal layers

              G = wiring channel width or length between centers of via pads above                    

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