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A Design Economics Horror StoryMay 7, 2020 | Rick Hartley, RHartley Enterprises
Estimated reading time: 3 minutes
Editor’s note: During a recent conversation with Rick Hartley, he shared one of his favorite PCB design horror stories. This is a cautionary tale about what can happen when design teams place too much faith in app notes and do not follow cost-aware design techniques. Enjoy!
When I first went to work at a company in 2003, I was asked to look at a circuit board that was not working properly; the few they did get to work had major EMI problems. I discovered they had placed the parts badly so that routing the memory lines to be even close to a similar length was going to be nearly impossible.
The engineer who did the schematic looked at the app note for the particular memory that was used with this processor, which stated, “Route all the memory lines within the same length of one another at ±50 mils.” The engineer thought, “50 is good, and 25 is even better,” so he put a note on this schematic that the memory lines should all be the same length at ±25 mils. What’s really interesting is that engineers often don’t understand that inner and outer layers propagate at different rates. If you make all the lines the same length, they don’t have the same propagation time, and they don’t match anyway.
Then, they farmed out the layout. And the people who did the layout—because of the poor positioning of components—couldn’t get all the lines routed anywhere close to the same length without a ton of tromboning or serpentining of the memory lines. They ended up with 14 routing layers, and the only way they could get it to the thickness required was to make it an 18-layer board. They had an 18-layer board with only four plane layers and 14 routing layers. Anybody who knows anything about design is already thinking, “How could this possibly work?”
It all happened because of this overabundance of length-matching. To make matters worse, they had to have 65 ohms impedance on some of the lines because there was a PCI bus on the board. In order to get the dielectric constant—with these very thin dielectrics— low enough to hit the target impedance, they had to go to Rogers 4000 series material (at 6 to 8 times the cost of FR-4). The bare boards were seven by nine inches, and they were going to cost an estimated $235 each in quantities of 1,000 at a time. Again, most of the boards didn’t work, and the few that did work failed EMI testing and were expensive.
I looked at the board and realized what the problem was. I asked the engineer why he put that note on the schematic. And he said, “It was in the app note. I figured they knew what they were talking about.” I asked, “Did you do a timing analysis?” He replied, “You know what management around here is like. We never have time for things like that.” I said, “Do you have time now to do a timing analysis?”
The engineer came back to me a day later and said, “By my calculation, we have about ±200–300 picoseconds of available skew.” I asked him, “Do you know how much that is in terms of length? It’s somewhere between two and three inches. Let’s even call it an inch. That means you could have made all these memory lines the same length ± 1inch, and they would have all worked.”
He exclaimed, “Bull. I don’t believe it.” I said, “Well, we are going to prove it to you!” We stripped away the routes, repositioned the components to make things route properly, routed the board with no line matching at all, and checked them when we were done, and they were all within an inch of the same length. We did no serpentining at all. We made a 10-layer board out of it instead of an 18-layer board with six routing layers and four plane layers.
It worked perfectly. It passed EMI testing, and the price dropped to $34 per board from $235 per board. That’s what happens when people blindly follow app notes.
Close-up of the original 18-layer board showing an abundance of tromboning.
This article originally appeared in the April 2020 issue of Design007 Magazine.
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