Cadence EDA Solutions, IP Optimized for Intel Process and Packaging Technologies
February 8, 2022 | Cadence Design Systems, Inc.Estimated reading time: 1 minute

Cadence Design Systems, Inc. announced it has joined the new Intel Foundry Services (IFS) Ecosystem Alliance to support mutual customers with the development and delivery of innovative system-on-chip (SoC) designs. As a member of the alliance, Cadence is advancing adoption of Intel process and packaging technologies and Cadence state-of-the-art digital, custom/analog, verification and advanced IC packaging EDA solutions, along with Cadence Design, Verification and Tensilica IP. Using Intel and Cadence technologies, customers can accelerate time to market while reducing design barriers, risk and costs.
There are several benefits to joining the IFS Ecosystem Alliance. Cadence will have early access to process and advanced IC packaging roadmaps, process design kits (PDKs) and technical training. This allows the Cadence R&D teams to fine-tune EDA tools and IP for the Intel portfolio of process and packaging technologies so customers can meet power, performance and area (PPA) requirements.
“We’re collaborating with world-leading partners like Cadence to ensure our customers have access to a robust, comprehensive design ecosystem, process technologies, advanced packaging technologies and manufacturing capabilities,” said Dr. Randhir Thakur, president of IFS. “Cadence is constantly developing new solutions and IP to stay in front of customer demands, making them a critical ecosystem partner that aligns with our mission to address the growing global demand for chips with breakthrough SoC design technologies.”
“By joining the IFS Ecosystem Alliance, we’re demonstrating our commitment to ensuring that customers can quickly become proficient using Cadence solutions and IP supporting Intel process and packaging technologies,” said Dr. Anirudh Devgan, president and CEO of Cadence. “Our customers are under extreme pressure to deliver power-efficient and performance-optimized SoCs, and the Cadence and IFS collaboration lets our customers innovate with confidence.”
Cadence tools and IP support the company’s Intelligent System Design strategy, which enables customers to achieve SoC design excellence.
Suggested Items
Robust AI Demand Drives 6% QoQ Growth in Revenue for Top 10 Global IC Design Companies in 1Q25
06/15/2025 | TrendForceTrendForce’s latest investigations reveal that 1Q25 revenue for the global IC design industry reached US$77.4 billion, marking a 6% QoQ increase and setting a new record high. This growth was fueled by early stocking ahead of new U.S. tariffs on electronics and the ongoing construction of AI data centers around the world, which sustained strong chip demand despite the traditional off-season.
Cadence Advances Design and Engineering for Europe’s Manufacturers on NVIDIA Industrial AI Cloud
06/13/2025 | Cadence Design Systems, Inc.At NVIDIA GTC Paris, Cadence announced it is providing optimized solutions for the world’s first industrial AI cloud in collaboration with NVIDIA.
Zuken Autorouters Embrace Collaborative AI
06/12/2025 | Andy Shaughnessy, Design007 MagazineMaybe you’ve never liked autorouters; if so, you’re not alone. As Andy Buja, Zuken’s technical account manager for PCB Solutions, admits, autorouters are not perfect. But today’s autorouters allow designers a greater level of control than ever before, especially routers that incorporate collaborative AI.
Bridging the Knowledge Gap in Test: A Conversation with Bert Horner
06/11/2025 | Barry Matties, I-Connect007Bert Horner is a seasoned industry veteran and co-creator of The Test Connection, Inc. (TTCI), a test and inspection company spanning over 45 years. In this candid conversation, Bert reflects on the challenges our industry faces with the retirement of career professionals and the subsequent loss of critical tribal knowledge. As he unveils The Training Connection’s innovative training initiatives, Bert emphasizes the importance of evolving educational programs that align with industry needs, particularly in design for test (DFT), and sheds light on strategies being implemented to foster the next generation of engineers.
The Shaughnessy Report: Planning Your Best Route
06/10/2025 | Andy Shaughnessy -- Column: The Shaughnessy ReportDesigners don’t like autorouters, period. In my 26 years of covering PCB design and EDA tools, I’ve met about 25 designers who admit to using autorouters regularly. Two of these, Barry Olney and Stephen Chavez, have articles in this issue. If experts like these use routers, why haven’t you tried one?