The Shaughnessy Report: Showing Some Constraint
Elementary, Mr. Watson: Rein in Your Design Constraints
Target Condition: Are Autorouters Friend or Foe?
Does Copper Pour on a Signal Layer Decrease Signal-To-Signal Isolation?
April 7, 2022 | Steve Hageman, Analog HomeEstimated reading time: 1 minute
Does putting a ground pour on PCB signal layers make the isolation better or worse? It can go either way, but with the proper knowledge and application, this technique will improve your designs.
In this article, I’ll discuss how to simulate trace-to-trace isolation with true electromagnetic simulation software. We’ll also cover a variety of rules of thumb that can help you stay away from trouble.
Fact or Fiction?
Recently an acquaintance told me, “I have heard that putting a copper pour on a signal layer between traces actually makes the isolation between the traces worse.” I grabbed one of my RF boards and said, “If that is so, then how do all these RF boards that I have done with co-planar waveguide over ground manage to function? They all have copper pours on the signal layer, and they work to very high frequencies.”
Since co-planar waveguide over ground (CPWG), which is essentially “pouring copper on a signal layer,” is used for a lot of RF work, and is proven to work for very high-performance RF circuits, how did this contradictory opinion catch on in the industry?
To investigate this, I used a one-inch section of 50-ohm microstrip consisting of an aggressor trace from ports 1 to 2 and a victim trace running in parallel from ports 3 to 4. I used typical values for the dimensions as might be on a real PCB. The trace width is 20 mils, with a spacing of 60 mils from center to center, over an FR-4 substrate, 9.5 mils thick, with a modeled Er of 4.4.
To read this entire article, which appeared in the March 2022 issue of Design007 Magazine, click here.
Share on:
Suggested Items
Copper Price Surge Raises Alarms for Electronics
07/15/2025 | Global Electronics Association Advocacy and Government Relations TeamThe copper market is experiencing major turbulence in the wake of U.S. President Donald Trump’s announcement of a 50% tariff on imported copper effective Aug. 1. Recent news reports, including from the New York Times, sent U.S. copper futures soaring to record highs, climbing nearly 13% in a single day as manufacturers braced for supply shocks and surging costs.
I-Connect007 Editor’s Choice: Five Must-Reads for the Week
07/11/2025 | Andy Shaughnessy, Design007 MagazineThis week, we have quite a variety of news items and articles for you. News continues to stream out of Washington, D.C., with tariffs rearing their controversial head again. Because these tariffs are targeted at overseas copper manufacturers, this news has a direct effect on our industry.I-Connect007 Editor’s Choice: Five Must-Reads for the Week
Digital Twin Concept in Copper Electroplating Process Performance
07/11/2025 | Aga Franczak, Robrecht Belis, Elsyca N.V.PCB manufacturing involves transforming a design into a physical board while meeting specific requirements. Understanding these design specifications is crucial, as they directly impact the PCB's fabrication process, performance, and yield rate. One key design specification is copper thieving—the addition of “dummy” pads across the surface that are plated along with the features designed on the outer layers. The purpose of the process is to provide a uniform distribution of copper across the outer layers to make the plating current density and plating in the holes more uniform.
Trump Copper Tariffs Spark Concern
07/10/2025 | I-Connect007 Editorial TeamPresident Donald Trump stated on July 8 that he plans to impose a 50% tariff on copper imports, sparking concern in a global industry whose output is critical to electric vehicles, military hardware, semiconductors, and a wide range of consumer goods. According to Yahoo Finance, copper futures climbed over 2% following tariff confirmation.
Happy’s Tech Talk #40: Factors in PTH Reliability—Hole Voids
07/09/2025 | Happy Holden -- Column: Happy’s Tech TalkWhen we consider via reliability, the major contributing factors are typically processing deviations. These can be subtle and not always visible. One particularly insightful column was by Mike Carano, “Causes of Plating Voids, Pre-electroless Copper,” where he outlined some of the possible causes of hole defects for both plated through-hole (PTH) and blind vias.