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Webinar Review: Thermal Integrity of High-Performance PCB DesignAugust 1, 2022 | Andy Shaughnessy, Design007 Magazine
Estimated reading time: 2 minutes
Electrical and mechanical engineers may be working on the same product development teams, but they speak different languages, and they have completely different objectives. As a result, these folks almost never use the same software tools.
But Cadence’s new Celsius Thermal Solver is an exception to the rule. In a new CadenceTECHTALK webinar, “How Static and Dynamic IR Drop Analysis Can Help PCB Designs and Challenges,” product manager Melika Roshandell and SerDes SI/PI engineer Karthik Mahesh Rao explain how the EE and ME can both use the Celsius Thermal Solver to achieve their disparate objectives—at the chip and package/board levels.
Melika discusses the solver’s capabilities on the PCB and packaging side, which are accessible during pre-layout stages of the design cycle. Built on FEA and CFD engines, the solver can identify Joule heating on boards and packages, and help determine copper density, component spacing, and proper placement and size of thermal vias. She compares the results of the solver’s dynamic IR drop analysis with DC analysis, which only works with uniform temperature. Melika also points out the differences between typical thermal simulation and the solver’s electrothermal co-simulation.
Karthik then takes over, demonstrating electrothermal co-simulation by importing an entire CAD file into the Celsius environment. He utilizes PowerTree technology to organize heat sources and heat sinks—definitions, model names, target impedance constraints, etc. He places probes at different points on the PCB and tracks the transient results of components across various points of time. He shows how to trace power loss across each layer across time, and changes in power distribution as well. The 3D modeling capability depicts any potential hot spots on the board.
To illustrate how this PCB would operate in the real world, Karthik switches to the CFD analysis environment and places the design inside an enclosure. He adds a heat sink to one of the thermally problematic packages, and a cooling fan on the side of the enclosure, then traces the cooling flow across the component and board. Karthik closed with examples of the more comprehensive results attained through transient electrothermal co-simulation vs. traditional steady state analysis.
The Celsius Thermal Solver continues the “shift left” of signal integrity horsepower into the front end of the design cycle, and it offers functionality that will appeal to electrical and mechanical engineers. Maybe EEs and MEs will eventually speak the same language after all.
Melika and Karthik pack quite a bit into this half-hour webinar. If you’re dealing with thermal challenges in your high-speed PCB designs, you’ll want to check out the CadenceTECHTALK, “How Static and Dynamic IR Drop Analysis Can Help PCB Designs and Challenges.”
- Shift Left: Moving Multiphysics into the Mainstream by Sherry Hess
- Successful Thermal Management of 3D-ICs: Accurate, Fast, Efficient, and Scalable with Celsius by Melika Roshandell
- The System Designer's Guide to... System Analysis: Electromagnetic Interference and Thermal Analysis of Electronic Systems by Brad Griffin
- The Cadence System Design Solutions Guide
- “Cadence Provides ‘Clarity’ in Design Tool” Interview with Brad Griffin, Design007 Magazine, (July 2022)
There has always been pressure to reduce line and space as we have seen the bleeding edge technology go from 8 mils to 5 mils and then to 3 mils. The difference between “then” and “now” is that the prior advancements, for the most part, used the same processes, chemistry and equipment going from 8 mils to 3 mils. But going from 3 mil to sub 1 mil trace and space is a quantum leap in printed circuit board (PCB) technology that requires a whole new set of processes and materials.
In a previous column, the critical process of desmear and its necessity to ensure a clean copper surface connection was presented. Now, my discussion will focus on obtaining a void-free and tightly adherent copper plating deposit on these surfaces. After the desmear process, the task is to insure a continuous, conductive, and void-free deposit on the via walls and capture pad. Today, there are several processes that can be utilized to render vias conductive.
Panasonic’s Darren Hitchcock spoke with the I-Connect007 Editorial Team on the complexities of moving toward ultra HDI manufacturing. As we learn in this conversation, the number of shifting constraints relative to traditional PCB fabrication is quite large and can sometimes conflict with each other.
MKS’ Atotech, a leading surface finishing brand of MKS Instruments, will participate in the upcoming IPCA Expo at Bangalore International Exhibition Centre (BIEC) and showcase its latest PCB manufacturing solutions from September 13 – 15.
Flexible circuit applications can be as basic as furnishing electrical interconnect between two conventional circuit board assemblies, or to prove a platform for placing and interconnecting electronic components. During the planning and pre-design phase of the flexible circuit, there will be several material and process related questions that need to be addressed. Most flexible circuit fabricators welcome the opportunity to discuss their customers’ flexible circuit objectives prior to beginning the actual design process.