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Forming Standards for Ultra HDIOctober 25, 2022 | Andy Shaughnessy, Design007 Magazine
Estimated reading time: 3 minutes
To get the latest news about ultra high-density interconnections (UHDI), we checked in with Jan Pedersen, NCAB Group’s director of technology. Jan is co-chair of IPC D-33AP, and a great source of overall DFM expertise as well. We asked him to give us a snapshot of UHDI in the industry, where we’re headed, and what this means to PCB designers.
Q: How do you define ultra HDI? What is the cutoff in mils or microns?
A: UHDI is defined in the IPC UHDI task group as a PCB design with lines and spaces below 50 microns, dielectric thickness below 50 microns, and microvias below 75 microns. These are attributes beyond the existing IPC-2226 Producibility level C.
Q: Tell us about your work on IPC’s UHDI committee. What are you working on right now? Are the standards keeping up with UHDI technology?
A: The UHDI task group has now developed a basic description and parameters. We are ready to hand over our work to the next group at IPC to start building the standards structure, starting with design, followed by performance and acceptance standards.
The standards will keep up with UHDI technology, but this will need our full attention for the standard to reflect current production capabilities globally.
Q: Much of the ultra HDI we see involves semi-additive technology. Can you clear up the differences between mSAP and A-SAP, and what it means to designers and design engineers?
A: SAP stands for semi-additive processes, and there are a few versions out there such as mSAP and A-SAP. We call them semi-additive because they all start with a thin layer of copper before creating the circuitry. This can be either from a copper-clad material, similar to what we use in traditional PCB manufacturing but with thinner copper, or a non-clad material where the PCB factory plates the seed layer. The difference between mSAP and A-SAP is the thickness of the seed layer where mSAP starts with a copper layer, typically 3–4 microns, while A-SAP starts from an unclad material activating the surface, adding a very thin chemical copper layer of less than 1 micron. Then both processes use photolithographic methods to plate up copper traces to around 20-micron thickness before flash etching the seed layer. Basically, the thickness of the seed layer, as we see with A-SAP, is the main factor for the process to create thinner traces.
Q: How is designing in the ultra HDI arena different from designing a typical PCB? What are some of the hurdles?
A: Designing ultra HDI is a challenge today because of a lack of standards, both for PCB production and material availability. The big hurdle today is fabrication availability. There are processes and some materials available, but very few PCB factories can offer anything below 40-micron trace and space. Some factories claim to offer UHDI, but that is very often only down to 35- to 40-micron traces, while the components you want to use requires traces and spaces below 30 microns.
Q: Are there any resources—books, websites, instructors, etc.—for UHDI design techniques?
A: For designers who want to learn more about UHDI, there are a limited number of resources. I would start with Tara Dunn’s Altium blogs and her I-Connect007 columns, which often cover semi-additive and UHDI. Anyone considering moving into ultra HDI should follow the NCAB blogs, available on our website and on LinkedIn. Read everything that you can.
Q: What advice would you give designers who are considering moving into UHDI?
A: The best advice I can offer is to find a supplier and be sure that you design within their capabilities. NCAB has a plan to be providing high-mix, low-volume UHDI starting as early as 2023. Today all factories that offer less than 35-micron traces have extremely long lead times. Not to sound commercial, but NCAB Group has a clear plan to change that. We are not there yet but will be very soon.
I am leading the NCAB Technical Council, and one of the focus teams is working actively with ultra HDI. As soon as we have a factory that can offer shorter lead times on UHDI, we will develop design guidelines and webinars, and provide workable parameters for designers. We need safe parameters to secure manufacturing yields and product quality from the start. It is paramount for NCAB Group to be transparent about what we can offer and how ready we are with new technologies.
This interview originally appeared in the October 2022 issue of Design007 Magazine.
The "Global Copper Clad Laminates Market (by Type, Application, Reinforcement Material, & Region): Insights and Forecast with Potential Impact of COVID-19 (2023-2028)" report has been added to ResearchAndMarkets.com's offering.
The SCHMID Group, a global solution provider for the high-tech electronics, photovoltaics, glass and energy systems industries, will be exhibiting at productronica in Munich from November 14 – 17, 2023.
The topic of intrinsic copper structure has been largely neglected in discussions regarding the PCB fabrication quality control process. At face value, this seems especially strange considering that copper has been the primary conductor in all wiring boards and substrates since they were first invented. IPC and other standards almost exclusively address copper thickness with some mild attention being paid to surface structure for signal loss-mitigation/coarse properties.
At PCB West, I sat down for an interview with John Andresakis, the director of business development for Quantic Ohmega. I asked John to update us on the company’s newest materials, trends in advanced materials, and the integration of Ticer Technologies, which Quantic acquired in 2021. As John explains, much of the excitement in materials focuses on laminates with lower and lower dielectric constants.
Printed circuit board (PCB) reliability testing is generally performed by exposing the board to various mechanical, electrical, and/or thermal stimuli delineated by IPC standards, and then evaluating any resulting failure modes. Thermal shock testing is one type of reliability test that involves repeatedly exposing the PCB test board to a 288°C pot of molten solder for a specific time (typically 10 seconds) and measuring the number of cycles it takes for a board’s copper layer to separate from the organic dielectric layer. If there is no delamination, fabricators can rest assured that the board will perform within expected temperature tolerances in the real world.