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The Shaughnessy Report: Silicon to Systems—The Walls Are Coming DownAdvanced Packaging Means Advanced Routing Issues
January 26, 2023 | Kris Moyer, IPCEstimated reading time: 1 minute
In today’s ever-shrinking world of electronics designs, the use of BGA parts with very fine pitch features is becoming more prevalent. As these fine-pitch BGAs continue to increase in complexity and user I/O (number of balls), the difficulty of finding escape routes and fan-out patterns increases. Additionally, with the shrinking of silicon geometry leading to both smaller channel length and increased signal integrity issues, some of the traditional BGA escape routing techniques will require a revisit and/or adjustment to allow for not only successful fan-out, but also successful functioning of the circuitry of the BGA design.
Historically, BGAs could be routed using traditional full through-via structures, with dog-bone traces off the BGA pad. These BGAs were typically 1.27 mm in pitch and had sufficient clearance between the pads to place a Class 3 Level A via without violating any design rules. Additionally, the feature sizes of these packages were sufficient to fabricate in 1-ounce copper without any issues. With increases in chip complexity and I/O density, most BGA packages are now 1 mm or smaller pitch, with some packages as small as 0.4 mm pitch. With these finer pitch packages, it is no longer possible to use traditional full-thru via structures under the BGA. This, in turn, will require the use of sequential lamination and micro-via structures in order to successfully escape route the BGA. Figure 1 shows a comparison between the package and feature sizes of 484-ball 1 mm pitch BGA (U100) and a 100-ball 0.4 mm pitch BGA (U101).
First, we look at the 1 mm pitch part, then evaluate what it will take to escape all balls to the outside perimeter of the BGA. For this evaluation, we will only consider the use of stacked microvias. Staggered microvias will also work, but require significantly more board area. Additionally, the stackup will assume dual stripline for all internal signal layers.
To read this entire article, which appeared in the January 2023 issue of Design007 Magazine, click here.
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