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Broadcom PCB Design: Miniaturization on the Cutting EdgeJune 15, 2015 | Andy Shaughnessy, PCBDesign007
Estimated reading time: 3 minutes
I recently attended the Orange County Designer's Council “Lunch and Learn” meeting, held at the Broadcom offices on the campus of the University of California, Irvine. Afterward, I sat down with Scott Davis, CID, the senior manager of PC board design at Broadcom, to discuss the company’s savvy PCB design department and their approach to PCB design.
Andy Shaughnessy: Scott, tell us a little about yourself and the design team you manage.
Scott Davis: I've been in the industry since 1996 when I actually joined a historic company, Praegitzer Industries. It was part of the Praegitzer design group that started the numerous acquisitions and transfers throughout the history of Tyco, the e2E Corporation, and the acquisition of Plexus Corporation. I moved with them from Oregon to Colorado, and then in 2007 I was informed about the position here at Broadcom. I have been here almost eight years. I'm managing a team of about 40. These people are designers, along with a CAD library team and our two resources that run Valor full time. This is a global team. We have 11 people in Singapore, one person in Canada, one person in India, and the rest of the remaining folks here in America, mainly in California.
Shaughnessy: Is that 40 PCB designers?
Davis: It's managers, designers, librarians, and Valor operators, a combination of all of the above.
Shaughnessy: So, you all rely on Valor?
Davis: We love Valor and the fabricators love the Broadcom packages for fabrication because they don't spend any time in engineering. They go right to the floor for production and we run every single design through Valor. The reason for that is we have two CAD tools. We're using the Mentor Graphics tools and we're using the Cadence tools, but we want our output packages to be consistent, including PDFs, Gerbers, .tgz files, pick-and-place files, etc. We find that Valor provides that third-party platform in order for us to quickly and automatically create those deliverables which we then load into our ERP systems for release to the suppliers.
Shaughnessy: What kind of design challenges are your teams facing?
Davis: Certainly the challenge we have as a world leader in semiconductors is the breadth of technology that we see. We see everything from two layer boards to 24-layer boards. We have a group here doing ATE boards. We're doing simple Bluetooth boards, WiFi boards, high-speed networking boards. So I think that the challenge we have is that, in a large design group, it's good for the designers to get that variety, and that keeps their skill sets really sharp on a variety of technologies. We're not doing power supply after power supply after power supply. You may work on a WiFi board one week and you may work on a cable set-top box or a cable modem the next week. That's one of the dynamic aspects of my group: the variety of technology that Broadcom brings to the table. It’s unique to the industry.
Shaughnessy: We surveyed our readers last month, and some of the designers said that it's getting to be less fun because there's so little real estate and they're just running out of space on the board. Is that a real problem for you too?
Davis: Yes, it's a real problem with the miniaturization of the WiFi circuits and the RF circuits. Certainly cellular telephones and any kind of 4G LTE and the new technologies that are coming up are just getting smaller and smaller. We are seeing 0.35 mm packages, 0.2 mm packages, so you're forced into these HDI, almost completely three-dimensional models that become very difficult to even realize or get a picture of when you first load your schematics and associate it to your board layout. It's very challenging.
Shaughnessy: How small of a via can you design?
Davis: Of course we can design almost anything. The fabricators are typically limiting us in some cases to 4 mil mechanicals, certainly 6 mil is a real break point. But 8 mil mechanicals are not a problem. You can go pretty thick on that. Microvias, we're trying to push down to 4 mils with 8 mil pads. That's pretty tight, but we stay pretty much industry standard as far as Class 2 for our designs. High reliability for most consumer electronics is not that large of an issue. You're certainly not Class 3. Most of our material is still 370HR, except for our high-speed stuff. We are doing some exotic materials and pushing the envelope in the SerDes serial stream gigabits per second.
Shaughnessy: It sounds like you have a really fun job.
Davis: It's a great job. I love being a part of industry opportunities. I want to thank you and appreciate the time to talk to me today.
Shaughnessy: Thank you. It’s been a pleasure.
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Cadence Design Systems, Inc. announced that Samsung Foundry successfully taped out a 5G networking SoC design on the Samsung 5LPE technology using the Cadence® Quantus™ Extraction Solution and Tempus™ Timing Solution.
There are many ways, dozens to be sure, and most likely many more, to streamline a PCB design. My goal here is to pick a single-digit number of rules to abide by, that can be reasonably adhered to, and provide some bang for the buck. These rules are meant to reduce design scope creep, avoid PCB respins, and improve production yields.
Hirose has expanded its low-profile DF51K wire-to-board connector series to include a surface mount technology (SMT) version. Compatible with automated assembly processes, including pick-and-place machines, the DF51K SMT Series simplifies the assembly process and saves significant manufacturing time and cost.