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Systematic Estimation of Worst-Case PDN Noise: Target Impedance and Rogue WavesFebruary 1, 2016 | Istvan Novak, Oracle
Estimated reading time: 1 minute
In the dark ages of power distribution design, the typical advice was to use a bulk capacitor and one 0.1uF bypass capacitor for every power pin on the digital circuit. This was very unscientific, but served the industry reasonably well in low-density and low-speed circuits. As the designs got more demanding, the target impedance concept was developed . Using a target impedance, designers had a metric and a design goal to guarantee that the voltage transients stay within specified limits.
Strictly speaking, the target-impedance concept is valid only for flat self-impedance profiles; however, most of our practical designs do not have that luxury. With non-flat impedance profiles, the noise is different. Surprisingly and counterintuitively, keeping the same maximum impedance, the more we deviate from the flat impedance by pushing the impedance down in certain frequency ranges, the higher the worst-case transient noise becomes. This raises the question how to do a systematic design and also gives rise to speculations about rogue waves . But there is a systematic, fast and efficient way of calculating the worst-case noise for any arbitrary impedance profile.
The target impedance concept assumes that the power distribution network is hit by a series of current steps, each current step having a magnitude of DI and fastest transition time of ttr. If up to the BW bandwidth of the excitation the PDN impedance is Ztarget, the resulting voltage transients are within the DV limits.
To read this entire article, which appeared in the December 2015 issue of The PCB Design Magazine, click here.
Panasonic’s Darren Hitchcock spoke with the I-Connect007 Editorial Team on the complexities of moving toward ultra HDI manufacturing. As we learn in this conversation, the number of shifting constraints relative to traditional PCB fabrication is quite large and can sometimes conflict with each other.
In my last column, I discussed cutting-edge innovations in printed circuit board technology, focusing on innovative trends in ultra HDI, embedded passives and components, green PCBs, and advanced substrate materials. This month, I’m following up with the products these new PCB technologies are destined for. Why do we need all these new technologies?
Experience ViTrox's State-of-the-Art Offerings at SMTA Guadalajara 2023 Presented by Sales Channel Partner—SMTo Engineering09/18/2023 | ViTrox
ViTrox, which aims to be the world’s most trusted technology company, is excited to announce that our trusted Sales Channel Partner (SCP) in Mexico, SMTo Engineering, S.A. de C.V., will be participating in SMTA Guadalajara Expo & Tech Forum. They will be exhibiting in Booth #911 from the 25th to the 26th of October 2023, at the Expo Guadalajara in Jalisco, Mexico.
Intel announced one of the industry’s first glass substrates for next-generation advanced packaging, planned for the latter part of this decade.
I have been in and around circuit boards most of my life. I started 20 years ago in my family’s PCB shop, leaving after a couple of years to start my own software company. About a year ago, I returned to the family business, and the first thing I noticed was that nothing had really changed. We were doing the same things in the same way as the day I left. After talking to several experts in the industry, I realized it was worse than that: The manufacturing of PCBs had not changed in 70 years.