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Designers Notebook: PCB Designers Guide to Heterogeneous Chiplet Packaging

Integrating multiple chiplet elements on a single interposer or package substrate may be referred to as a multi-chip module, a hybrid IC, a 2.5D package, or simply an advanced package. Implementing chiplet technology will provide several advantages over the traditional, system-on-chip alternative. Each chiplet element is designed to be a building block with a specific function that is often common for multiple system-level products. Chiplet elements can also be sourced from multiple providers, even though they may be using alternative fabrication processes.

Common goals that product developers strive to achieve are improving performance, simplifying assembly processing, and for the companies that are producing hand-held, portable, and wearable electronics, minimizing product size. Achieving these objectives has been made possible through advances in semiconductor fabrication methods and innovative packaging technology. Until recently, the alternative to arranging and interconnecting individual semiconductor functions relied on integration, a process for combining multiple functions into a single “monolithic” die element. Developers found that by combining the CPU with all primary logic support utilities, a true heterogeneous system-on-chip (SoC) product was achievable. Technically, the SoC package accomplished two goals: Processing speed increased and it scaled down the overall circuit board area by integrating several supporting functions within a single package outline.

As the basic SoC morphed into the newer multiple core processor variations, the semiconductor developers realized that they would need a more efficient solution to support current and future generations of advanced computing products. Merging all the peripheral functions onto the same piece of silicon as that supporting the larger multi-core processor functions has resulted in an excessive increase in silicon area and, for some, unacceptable wafer processing defects. Here’s the thing: Defects in the CPU portion of the die are not uncommon. It happens, but when defects occur in any of the peripheral supporting functions, the whole element must be scrapped, even though the multi-core CPU is functioning perfectly.

High-Density Semiconductor Packaging Innovation
Breaking up the traditional SoC model, several developers have adopted a heterogenous packaging solution using chiplets, which isn’t a package type but part of a packaging architecture. With chiplets, individual die elements can be broken down into smaller pieces and mixed and matched as needed to emulate the multiple function monolithic SoC die. A chiplet is simply a small outline, silicon-based integrated circuit (IC) that contains a specific subset of functionality. The chiplet elements are designed to function in unison with other chiplets, sharing a common platform because the chiplet elements, typical of those illustrated in Figure 1, can be placed very close to one another, minimizing signal path lengths. The shorter path connecting the chiplet elements ultimately leads to enhancing the end product’s performance potential.

A primary benefit of adopting chiplets is that the cost of wafer fabrication is much lower than the monolithic multiple function die, delivers a higher yield than the single monolithic die variations, and each element can be pre-tested. The flexibility offered by chiplets also provides important design and development benefits. Because they can be customized and upgraded easily, chiplets allow manufacturers to rapidly adapt to changing market conditions or new technological developments. They also simplify the production process by reducing the time and steps required to design and manufacture complex, application-specific SoCs.

So, where does the circuit board designer fit into this emerging package technology swing?

Many challenges come with interconnecting chiplets, especially in the context of commercial applications and scalability. On the other hand, they offer a promising solution to some of today’s most pressing chip design issues. Much like the traditional printed circuit board as the basic interconnect method for electronic products, the heart of the system-in-chip (SiP) variation is the interposer-substrate, the silicon or glass-based platform that glues everything together (Figure 2).

Circuit interconnect and land pattern geometry for the processors and chiplet elements are defined in millimeters and micro-meters (or microns), significantly smaller than the traditional surface mount configured circuit board; CAD tools to support interposer development are already in place.

Although silicon wafers or glass panels will be the preferred base platform for the highest density applications, there are inorganic materials that will accommodate the merging of chiplet die elements with a more relaxed density. In any case, it’s simply a matter of scaling.

Status of Standards for Chiplet Elements
The industry chiplet standards are still being ironed out, but there are two major proponents: the Universal Chiplet Interconnect Express (UCIe) Consortium and the Joint Electronic Device Engineering Council (JEDEC). Activities within the JEDEC JC-11 subcommittee’s scope include all aspects of the mechanical design, integration, interoperability, and standardization of all semiconductor devices. The organization’s responsibilities include generating design guidelines, standardized measuring methods for mechanical features, and mechanical outlines for commercial microelectronic packages and assemblies. The member-supported working groups also develop mechanical, environmental, and ergonomic performance specifications, recommend land pattern geometry, and establish the designators for identifying semiconductor device packages.

While several semiconductor developers have already established their own procedures for integrating their proprietary chiplet families, JEDEC member companies have initially targeted standards development for high-capacity memory, standards for stacked DRAM, as well as open compute platform (OCP) as part of their open domain-specific architecture initiative. These standards will guide the chiplet builders in developing an electronically standardized chiplet part description to make it easier to create a chiplet-configured system-in-package (SiP) design. By using chiplets, the ultimate goal is to reduce product development times and eliminate wafer process deficiencies by integrating pre-developed and electrically certified (KGD) dies onto an interposer.

Chiplet standards development activity is well underway, although the idea of a LEGO brick's format, with the same size die and a universal terminal pattern for interface (that some predicted during the early stages of development), will not be practical.

So, a chip maker may have a menu of modular dies, or chiplets, in a library similar to the traditional plastic-encased, pre-packaged semiconductors. Using an uncased die, the designer is able to mix-and-match the chiplets and connect them using an ultra-high-density, die-to-die interconnect scheme only possible with silicon and glass interposers. To ensure that chiplets supplied from different manufacturers can work together, significant issues must be defined. Standards will need to describe the physical connectivity required between chiplet elements, and define compatible signal levels, operating voltages, and data transfer rates as well as digital compatibility aspects. Also required: the number of lanes in a bus, the coding sublayer for error correction, and how individual devices will know to automatically connect and exchange data with one another.

Change in Semiconductor Package Strategies
The industry front runners agree that as the electronics industry moves forward, more and more products will reflect this chiplet building-block approach for highly complex semiconductor packaging applications. Every major foundry has a technology roadmap addressing the interconnect densities for both the 2.5D and 3D integration. These roadmaps will also forecast the progression of both logic and memory stacking and logic element stacking. While many challenges come with implementing chiplet elements, especially in the context of commercial applications and scalability, they offer a promising solution to some of today’s most pressing chip design issues.

With chiplet technology gaining momentum, it’s only natural that many big players in the industry are starting to get involved. Global Foundries and Samsung, for example, are two major companies at the forefront of this trend, each working on their own solutions to the chiplet challenge while Intel Corporation, AMD, Qualcomm, ARM, TSMC, and Samsung are working together on defining new standards for chiplet-based CPUs. 

Major Participants in Chiplet Packaging Innovation
Intel already has the pieces in place to develop these chiplet-based products. Key criteria, known-good dies, EDA tool refinement, die-to-die interconnect technologies, and a sustainable manufacturing strategy.

AMD is also actively researching and developing chiplet technology. The company has already released processors that use chiplet-based architectures (Figure 3).

IBM is a leading provider of advanced semiconductor technologies and is actively working on chiplet technology. The company has developed a chiplet-based architecture for its power processors and is also researching the use of chiplets in other applications.

TSMC is a contract semiconductor manufacturer and is actively researching and developing chiplet technology. The company has announced plans to use chiplet-based architectures in its future processors.

Samsung is actively researching and developing chiplet technology. The company has already released processors that use chiplet-based architectures.

GlobalFoundries is a contract semiconductor manufacturer and is actively researching and developing chiplet technology. The company has announced plans to use chiplet-based architectures in its future processors.

SK Hynix is a major provider of memory and storage solutions and is also actively researching and developing chiplet technology.

Micron is a leading provider of memory and storage solutions and is actively researching and developing chiplet technology.

Qualcomm is active in the mobile chip market and is researching and developing chiplet technology. The company has announced plans to use chiplet-based architectures in its future processors.

Huawei is a leading provider of telecommunications equipment and is also actively researching and developing chiplet technology. The company has announced plans to use chiplet-based architectures in its future processors.

Xilinx specializes in the design and development of FPGAs (field programmable gate arrays) and other types of programmable logic devices.

With continued development and innovation, the electronics industry can expect to see more widespread use of chiplet concepts sooner than later.

References

1. “Chiplets and Heterogenous Packaging Are Changing Design and Analysis,” a white paper by John Park, Cadence Design Systems, 2020.

This column originally appeared in the July 2023 issue of Design007 Magazine.