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Quiet Power: The Effect on SI and PI Board Performance

In signal and power integrity (SI and PI), we would ultimately like to see a reasonable agreement between the predicted or simulated and the measured performance of our circuits. Real-world measurements will always contain errors and usually show a distorted replica of the true behavior of the device under test (DUT). Real measurements always show more than just the behavior of the DUT. Even if we don’t consider random noise and random errors, in the measured data we have contributions from instrument, cable, and probe errors (just to name a few) that our calibration could not completely remove.

Simulations work differently: They always show less—an incomplete picture of the DUT—simply because there is no way for us to include every detail in our models practically. Not to mention the details that we may not even know about. In simulations, our first question is how to select and set up the models and how to adjust the simulation tool settings so that we get the correct and expected results. But simulations will include only those details that we set up and specify in our simulation model.

This is true for relatively well-known parameters, such as the dielectric constant and loss tangent of laminates, and for other parameters that we tend to describe with a range of fitted models, such as surface roughness. Dimensional tolerances fall into this category. They can be considered in simulations, for instance, by doing statistical margining of the dimensions. However, in high-speed interconnects there are so many geometry details that determine the channel performance, that simulating a meaningful number of combinations becomes daunting. One interesting case is related to backdrilling the unwanted via stub on high-speed channels. If the backdrilled hole is not concentric to the via barrel that we want to remove, there is a chance that a sliver of the barrel remains (Figure 1).

Figure 1a is a properly backdrilled via. In Figure 1b, there is a visible misregistration of the backdrilled hole, leaving part of the original via barrel in place. The residual via barrel behaves similarly to a full via barrel; it creates a dip in the signal transmission. The frequency of the dip is inversely proportional to the length of residual barrel, and the depth and bandwidth of the dip depend on its shape. Usually, a narrower residual sliver means a narrower dip on the frequency plot.

Though this is clearly a manufacturing defect, it does happen occasionally because optical inspection of a high-aspect-ratio small hole is challenging. The length, width, and shape of any remaining barrel are highly statistical in such cases. Correlation can only be successful if we first find the defect and get the dimensions of the remaining barrel by further analysis.

The next example (Figure 2) is not the result of manufacturing defect; it can happen in any high-speed board. The case study1 described the impact of registration tolerances on connectorized differential pairs. Coaxial connectors today tend to be much bigger than our typical trace width in high-density high-speed boards, requiring us to start with uncoupled traces until we can bring the two traces closer to form a differential pair. This inevitably means that the immediate vicinity of the connector launch—though they may be mirror images of each other—will not be identical.

The close-up photo of the launch via shows a case where the manufacturing tolerance pushed the via barrel sideways, further away from the exiting trace. We can then expect (as it was verified) that the via barrel in the other launch will get closer to the exiting trace. This minute difference is enough to create the highlighted difference in the TDR response. For such cases, the suggested solution of the cited reference is to exit differential launches with short parallel trace sections before the traces take a turn.

The third illustration, which is related to assembly, is reproduced2 and is shown in Figure 3. Many of our complex packages today use a ball grid array (BGA) connection to the printed circuit board. These tiny solder balls are usually placed on a regular grid with a center-to-center spacing called the pitch. For big chips, 0.8 mm and 1.0 mm pitches may be common. For smaller packages and higher speeds, smaller pitches are available. When we route differential pairs through a package, it is a good idea to place the balls connecting the two legs of the differential pair on adjacent grid points and surround them with enough return (ground) vias.

Return vias help to keep the impedance better defined through the transition between the board and package and provide isolation to and from nearby signal and power connections. During the solder reflow process, depending on many factors, the size and shape of the solder balls will end up being slightly different. These solder balls, no matter how tiny they look, still tend to be bigger than the connecting via barrels and traces. Therefore, seemingly small absolute variations in geometry numbers may result in very noticeable impedance, insertion loss, and crosstalk performance differences. Reproduced2, Figure 3 shows the simulated performance as a function of solder ball dimensions.

Our final illustrations are related to power distribution. As opposed to the early days of electronic circuits, when carrying the power and ground connections around a board was done with wires or fat traces, to feed power-hungry chips consuming tens and hundreds of amperes today, we use power planes in our boards. When we define our stackup, the number and thickness (weight) of our power and ground layers, it is very useful to know a little bit about the processes of how printed circuit boards are fabricated.

To determine the current-carrying capability of a power-plane shape, we need to know the thickness and conductivity of the copper. Instead of thickness and conductivity, in the trade of copper foils , people use weight (you may hear about one-ounce or two-ounce copper) and method of production (electrodeposited or rolled/annealed copper). The recent “Mind Your Units” article3 is a reminder that units matter, and the units used for PCB fabrication and trade may be counter-intuitive.

How the PCB copper is patterned during fabrication will also influence the current-carrying capability. During wet etching, the sidewalls of traces and plane shapes will become tilted. On a single large plane shape, this may matter very little, but when we have large chips in a dense printed circuit board, we end up with a lot of perforation due to the many antipads around vias that do not connect to the particular plane. This becomes obvious under the cores of big chips, where alternating power and ground through-vias perforate the planes. If we do not consider the slanted sidewalls, we may end up with a too optimistic design. The illustration in Figure 4 is reproduced4. It shows the simulated voltage drop on the power plane of a high-current CPU rail, assuming vertical sidewalls and the more typical 60-degree sidewalls. The etch factor alone results in a 10% increase of end-to-end resistance, on top of the impact of the perforation itself.

Summary
We need to be aware of the basics of PCB fabrication and assembly because they have an impact on the high-speed, power integrity, and thermal performance of our boards.

References

1. “Increasing Broadband Interconnect Characterization,” EDICON 2018.
2. “A Case Study in the Development of 112 Gbps-PAM4 Silicon and Connector Test Platform,” DesignCon 2021.
3. “Mind Your Units,” Printed Circuit Design and Fab, Circuit Assembly, December 2023, p. 56.
4. “Etch Factor Impact on SI & PI,” DesignCon 2019.

This column originally appeared in the January 2024 issue of Design007 Magazine.