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IWLPC Technical Committee Announces Best Presentation & Papers Awards for 2016
February 15, 2017 | IWLPCEstimated reading time: 1 minute
The IWLPC Technical Committee is pleased to announce the Best of Conference, Best Presentation & Best Papers in WLP, 3D, MEMS and Manufacturing tracks as chosen by the technical committee and attendees based on technical merit, relevance, originality, knowledge of subject, quality of material, and quality of presentation.
Best of Conference Presentation - Paul Silvestri, Amkor Technology
“3D-TSV Assembly: Package Architectures and Trade-offs”
Best of Conference Paper - Allan Hilton, RTI International
“Wafer-Level Vacuum Packaging of Microbolometer-based Infrared Imagers”
Best of 3D Track Paper - Min Tao, Ph.D. Invensas
“BVA Enabled Low-Profile, High-Density Fan-Out Wafer-Level PoP”
Best of WLP Track Paper - Stream Chung, Chemleader
“Electroplated Nano Twinned Copper for Wafer-Level Package”
Best of MEMS Track Paper - Allan Hilton, RTI International
“Wafer-Level Vacuum Packaging of Microbolometer-based Infared Imagers”
Best of Manufacturing Track Paper - Gerard John, Amkor Technology
“A Practical Approach to Test Through-Silicon Vias (TSV)”
About IWLPC
IWLPC brings together the semiconductor industry's most respected authorities addressing all aspects of wafer-level, 3D, TSV and integrated system packaging.
Going into its 14th year, the IWLPC is co-produced by Chip Scale Review, the leading international magazine addressing the semiconductor packaging industry, and SMTA, the distinguished global association representing electronic assembly and manufacturing professionals.
The conference comprises three parallel technical tracks with two full days of presentations on wafer-level packaging, 3D integration, and MEMS development. Workshops, keynote speakers, and panel discussions are offered by world-class experts and enable attendees to broaden their technical knowledge. The technical program includes a two-day expo where 60+ exhibitors showcase their latest technologies and products. The conference provides a collective network of over 800 industry professionals, including vendors from leading semiconductor companies, foundries, and OSATS, as well as key technology, equipment, and materials suppliers in the exhibit area. Attendees will be inspired by the quantity and quality of the featured new developments and emerging technologies. The 14th Annual Conference will be held October 24-26, 2017 in San Jose, CA. For more information click here.
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05/08/2025 | Cherie Litson, EPTAC MIT CID/CID+There are many great books, videos, and information online about designing PCBs for RF circuits. A few of my favorite RF sources are Hans Rosenberg, Stephen Chavez, and Rick Hartley, but there are many more. These PCB design engineers have a very good perspective on what it takes to take an RF design from schematic concept to PCB layout.
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