Fresh PCB Concepts: Key Considerations for Reliability, Performance, and Compliance in PCBs
Elementary Mr. Watson: Navigating RF—A Glide Path Approach to Design Success
Designers Notebook: Layer Stackup Planning for RF Circuit Boards
PCB Signal Integrity Optimization Using X-ray Metrology
October 16, 2017 | Scott Jewler, SILICON VALLEY X-RAYEstimated reading time: 1 minute
Murphy’s Law
It happens again. A new backbone router/switch build or a line card upgrade is approaching completion when something goes wrong. The system won’t operate at the targeted data rate. Deadlines are looming and the root cause of the problem is buried somewhere in a big rack of electronic components. The integrated circuits were all speed tested prior to printed circuit board assembly. There must be a problem in the system assembly, but where?
For some time, control of printed circuit board manufacturing to specification has relied primarily on coupon tests. These are time-consuming and often poorly represent the live portion of a panel, much less a population of panels. Modifications to designs, variations in line and space widths, and misalignment of layers can occur without the supplier being aware of the impact these changes have on the system’s performance. Electrical test methodologies for bare boards are difficult to maintain, expensive, and provide limited information. Engineers are left to commit large amounts of money to board builds and cloud server manufacturing and hope the PCBs perform per design.
The challenge is getting harder
As the industry moves rapidly to full deployment of 28 Gbps backplanes, many cloud hardware and PCB manufacturers are just beginning to regain confidence that what they build will work as intended. But 56 Gbps backplanes are just around the corner, or already in the driveway for some companies. And line cards are not far behind. These faster data rates require even tighter design compliance and PCB process control.
Certainly, much of this battle will be fought on the design side. Single layer routing, sacrificial vias, and other techniques can mask PCB process variation. But is this the most desirable or cost-effective solution? The time is right for a new generation of metrology tools that will enable PCB manufacturers to build better products and for network designers to unleash the performance of their products without worrying about variances in as-built boards.
To read the full version of this article which appeared in the October 2017 issue of The PCB Magazine, click here.
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