-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueAdvanced Packaging and Stackup Design
This month, our expert contributors discuss the impact of advanced packaging on stackup design—from SI and DFM challenges through the variety of material tradeoffs that designers must contend with in HDI and UHDI.
Rules of Thumb
This month, we delve into rules of thumb—which ones work, which ones should be avoided. Rules of thumb are everywhere, but there may be hundreds of rules of thumb for PCB design. How do we separate the wheat from the chaff, so to speak?
Partial HDI
Our expert contributors provide a complete, detailed view of partial HDI this month. Most experienced PCB designers can start using this approach right away, but you need to know these tips, tricks and techniques first.
- Articles
- Columns
Search Console
- Links
- Media kit
||| MENU - design007 Magazine
Nine Dot Connects Nov. 29 Webinar: Spelunking in the Altium Schematic Preferences
November 21, 2017 | Nine Dot ConnectsEstimated reading time: Less than a minute
Join Nine Dot Connects on November 29 for a free webinar, "Spelunking in the Altium Schematic Preferences."
What’s interesting about the preferences in Altium Designer is that they provide options and flexibility, making the tool more customizable for the user. However, many of us do not go spelunking into the preferences because we do not feel we have full command of the tool, or we simply choose to accept the default settings. This defeats the purpose of the preferences.
It dawned on Nine Dot Connects that the preferences are a powerful feature of Altium Designer, but they are generally overlooked. They also realized that trying to show all the preferences in one hour would not allow the topic to be covered adequately. In this webinar, Nine Dot Connects' focus will be specific to the schematic preferences, and will demonstrate and explain all of these schematic preferences.
This free webinar will be held on November 29 at 2:00 pm Eastern.
To register for the event, click here.
Suggested Items
IPC Announces New Training Course: PCB Design for Military & Aerospace Applications
12/23/2024 | IPCIPC announced the launch of a new training course: PCB Design for Military & Aerospace Applications.
eCADSTAR Sets New Standards for Compact PCB Design with Etched Inductor Parts
06/12/2024 | ZukenZuken announces the 2024 release of eCADSTAR, Zuken’s next-generation PCB design system for small and medium businesses. The new release includes a number of improvements ranging from enhanced design reuse, simplified revision tracking and more robust schematic design.
Elementary, Mr. Watson: Ensuring Design Integrity
03/28/2024 | John Watson -- Column: Elementary, Mr. WatsonBack in February, many of us watched the "Big Game." It reminded me of the saying, “It's not how you start that is important, but rather how you finish." It is perfectly okay when you are talking about sports, you get off to a bad first half and need to recover in the second half. However, when it comes to PCB design, this is not a good practice. If things start badly, they usually don't recover. They continue down that same path, costing more money and losing design time.
The Pulse: New Designer’s (Partial) Guide to Fabrication
01/31/2024 | Martyn Gaudion -- Column: The PulsePCB designers fresh to the industry may think that once the schematic is loaded into CAD and routed out into XY data, the finished PCB is an “exact” copy of their XY data. That’s not an unreasonable assumption for basic designs. Here, I’ll outline some of a designer’s considerations related to signal integrity as designs become more complex.
Three Things to Improve High-Speed PCB Signoff, Part 2
09/27/2023 | Brad Griffin, Cadence Design SystemsAnother challenge for SerDes is losses within the channel design. At high speeds, dielectric material can be very lossy, making the appropriate selection of the right material, length, etc., critical for the channel. Many questions about stackup, trace widths, and height from the ground plane need to be defined up front. Simulating a signal with a topology explorer tool extracted from the design can be used to set up and run sweep parameters and push min/max length/spacing values into the Allegro schematic constraint manager (system capture).