Share on:

Share on LinkedIn Share on X Share on Facebook Share with email

Suggested Items

IPC Announces New Training Course: PCB Design for Military & Aerospace Applications

12/23/2024 | IPC
IPC announced the launch of a new training course: PCB Design for Military & Aerospace Applications.

eCADSTAR Sets New Standards for Compact PCB Design with Etched Inductor Parts

06/12/2024 | Zuken
Zuken announces the 2024 release of eCADSTAR, Zuken’s next-generation PCB design system for small and medium businesses. The new release includes a number of improvements ranging from enhanced design reuse, simplified revision tracking and more robust schematic design. 

Elementary, Mr. Watson: Ensuring Design Integrity

03/28/2024 | John Watson -- Column: Elementary, Mr. Watson
Back in February, many of us watched the "Big Game." It reminded me of the saying, “It's not how you start that is important, but rather how you finish." It is perfectly okay when you are talking about sports, you get off to a bad first half and need to recover in the second half. However, when it comes to PCB design, this is not a good practice. If things start badly, they usually don't recover. They continue down that same path, costing more money and losing design time.  

The Pulse: New Designer’s (Partial) Guide to Fabrication

01/31/2024 | Martyn Gaudion -- Column: The Pulse
PCB designers fresh to the industry may think that once the schematic is loaded into CAD and routed out into XY data, the finished PCB is an “exact” copy of their XY data. That’s not an unreasonable assumption for basic designs. Here, I’ll outline some of a designer’s considerations related to signal integrity as designs become more complex.

Three Things to Improve High-Speed PCB Signoff, Part 2

09/27/2023 | Brad Griffin, Cadence Design Systems
Another challenge for SerDes is losses within the channel design. At high speeds, dielectric material can be very lossy, making the appropriate selection of the right material, length, etc., critical for the channel. Many questions about stackup, trace widths, and height from the ground plane need to be defined up front. Simulating a signal with a topology explorer tool extracted from the design can be used to set up and run sweep parameters and push min/max length/spacing values into the Allegro schematic constraint manager (system capture).
Copyright © 2024 I-Connect007 | IPC Publishing Group Inc. All rights reserved. Log in