Estimated reading time: 11 minutes

The Proper Position to Take on Voids in Solder Joints

First, a quick update on the conclusion to our material pricing disparity study. Unfortunately, we have received "crickets" from the agencies that were contacted. In my opinion, this industry issue is too important to drop. So, we’ll keep digging for data. If any of you in our reading audience can contribute data or firsthand experiences concerning the price of assembly material in high labor rate regions, versus material pricing when the assembly is done remotely in low labor rate areas, please let me know. Of course, as suggested in a past column this issue becomes moot if the components begin to be manufactured in the same geographic location where they are assembled into products.

The many current reshoring efforts being undertaken in high labor rate regions make the issue crucial. This is especially true if the assembly activity is being done by a company which is of small or medium size, either an EMS (electronic manufacturing services) or an OPD (original product developer)—specifically, one that does not have multiple global assembly operations served by a central procurement capability.

On Solder Joint Voids—The Dilemma

In parallel to the continuing attempt to gather data that address the disparity in component cost between high- and low-labor rate assembly regions, in this column, we leap off the bandwagon into another thorny issue: solder joint voiding.

On the surface, it doesn't seem to be an issue: "No voiding permitted." That's easy. However, not so fast says Inspector John J. Fadoozle, America's #1 private eye. The number of variables involved in void creation is daunting and not as well understood as you might think, notwithstanding the hundreds of technical papers written on the subject. And, there will be voids.

The void acceptance criterion is ill defined and strongly tied to void locations, volume and size. In addition, void acceptance is largely a function of a product's end use—Class 1, 2 or 3? And, to make it worse it’s important to understand what type of component the solder joint in question is attaching to the circuit board (e.g. BGA, micro BGA, LGA, CSP, QFP, QFN, QFD, DCA, passive devices, etc.). What about stacked memory modules? Add to that, how are we measuring a solder joint’s void population and character? 2D, 3D? And, of what can be thousands of solder joints on a circuit board, which ones do we inspect? All of them? No, that’s time prohibitive. Then how many and which ones should we look at?

Now, if you think this is a knotty issue for an OPD who assembles the products they design, pity the poor EMS. They build other company’s products. Does their ODP customer bring a void spec to the table? Is it a requirement of the purchase order? Do they invoke the requirements of joint standard IPC-STD-001, which in turn invokes the requirements of industry standards—IPC 610 and IPC 7095? Or, do they look to their EMS for guidance on voiding acceptability?

If the product fails in the field because of a solder joint that has fractured, who carries the liability? Who underwrites the cost of establishing root cause for the failure?

Void Reduction at SMTA International

This column is being written a few weeks after this year's SMTA International in Chicago. I hope many of you had the opportunity to attend the conference. In lieu of a more responsive and timely post-secondary educational system, this annual event brings leading edge issues and production equipment to the attention of our real world electronic product assembly community.

At the conference I chaired a technical session entitled "Void Reduction." Here is the session description:

This session presents three papers that document the results of solder joint void studies. All three studies were performed to establish the causal relationships that exist between material selection and process environment variables and the reduction in solder joint voiding. The first paper addresses the effect of solder reflow environment, paste printing material and printing process variables. The second is the third part in a series of papers on voiding. It provides the results of a parametric study conducted to examine void reduction as a function of paste powder size, solder alloy and PCB surface finish when using QFN, BGA and LGA components. The third paper describes a new process technique that applies sinusoidal vibration to the circuit board during solder joint formation in order to reduce voiding.

I think it is significant that there were no papers that addressed what is an acceptable level of voiding based on empirical testing or analytic study. There was no session entitled "Acceptable Voiding." However, I believe IPC has a working committee that is tasked with updating the current industry specs. The message in the "Void Reduction" session as it was described in last month’s SMT Magazine, “Achieving the Perfect Solder Joint,” do everything possible to eliminate or at least minimize voiding. "Acceptable" voiding is left to specification organizations and colleagues that have attempted to quantify the issue. Most of these have focused on voiding in BGA solder joints. So, let's eliminate voiding.

Cost Consequences

What is the cost? I remember the "zero defect" obsession. A zero-defect rate for products being shipped is certainly a justifiable and necessary production requirement. However, in-process zero defects? Even a 6-sigma defect process translates to 3.4 DPMO (defects per million opportunities).

And, in the real world most electronic assembly operations aim for 5-sigma (233 DPMO) or even a 4-sigma (6,210 DPMO) defect rate. If there are 1000 solder joints (opportunities) per board, there will be about six board failures per 1000 at 4-sigma and less than one board failing per 1000 at 5-sigma—even less board failures if more than one defect is found per board considered. How much money are you willing to spend to wring out all but 3.4 in-process DPMO to attain 6-sigma? Of course, if the defects are random and not in the assignable cause category, no amount of money will identify their root cause.

Since we began this Jumping Off the Bandwagon column, we have stressed the competitive importance of high assembly yields to reduce labor content in high labor rate regions of the globe. And, with a first-pass in-circuit test (ICT) yield of 99.6% coupled with passing a functional test as the board’s final acceptance (4 failures per 1000 boards or 4,000 DPMB (defects per million boards—assuming 1 defect per failed board), it makes sense to eliminate the ICT. The functional test will identify the defective circuit boards. It doesn’t pay back to subject 4000 boards to ICT to find the four with defects.

Let’s start with this: The product team, whether they belong to an OPD or an EMS, should write a quality assurance plan (QAP) for each assembly. Unfortunately, today I find most people in the industry don’t even know the difference between quality assurance (QA) and quality control (QC).

The QAP must clearly state what the acceptance criteria is for voiding and the inspection plan that will be used to ensure this acceptance level is met. The plan may invoke industry standards as well as company standard operating procedures (SOP) and any specific quality requirements such as inspection sampling plans, both automated and manual.

In most cases the student who moves through the looking glass from the academic side to the real-world side has most likely never even heard the phrase "solder joint void."

Is History Repeating Itself?

A couple of firsthand experiences from the graveyard of forgotten favorites:

1. Do you remember tweakers? Before circuit board labor content became an issue (pre-low labor rate competition, circa 1983) and when component placement accuracy had significantly more variation than we have today, many board assembly lines stationed a tweaker(s) between the exit of the pick and place machine and entrance of the reflow oven. With tweezers in hand their job was to gentle center components that were not perfectly placed in the wet solder paste. So, if even one component was tweaked per board the true first pass yield was zero. This reactive process caused much unnecessary rework to be done. This is the risk with how we approach solder joint voids. However, the risk is much more serious and costly since it in post reflow rework.

2. I remember the beginning of the commercial use of SMT. Assembly processes were being refined and there was significant process uncertainty accompanying the use of these components—components that weren’t anchored to the PCB with a lead that went through the board with a plated-through barrel full of solder. This caused a cautious approach in permitting the use of this new technology in the military. The Air Force was seduced by the lighter weight. However, they needed to be persuaded that the use of SMT in their electronic equipment was at least as good as the traditional pin-in-hole (PIH) technology and did not reduce the reliability of the system.

When an aircraft testing the technology had its navigational system fail in flight, the flags went up. Upon opening the failed electronic assembly, a number of SMT components were found loose, rattling around in the bottom of the chassis. Uh oh! Clearly the new component technology was not as robust as the tried and true through-hole technology. Or, was it? What was the root cause of the solder joint failures? It turns out it wasn’t anything inherent about SMT technology. In fact, an objective comparative look at the technology suggests that all things being equal using SMT should result in a more reliable assembly—less mass and a lower center of gravity. These characteristics result in a component-to-board assembly with a higher natural frequency. Consequently, there is less chance of the attachment going into resonance and resulting in a solder joint failure from the mechanical stresses induced by vibration and fatigue. Performance in shock and temperature environments should be better as well. The thermal stress developed between two different materials is proportional to the change in temperature, difference in thermal coefficient of expansion between the two materials (TCE), and the initial length of the interface.

So, what was it? In politics, a favorite catch phrase is: "It's the economy, stupid." In this case, we say, "It's the process, stupid." Many independent studies have linked solder joint mean-time-to-failure (MTTF) to the temperature the solder is exposed to during the assembly process. In this case the peak temperature and temperature duration caused the solder joint embrittlement. (Think of integrating the time/temperature reflow profile—effectively, summing the total thermal energy applied to solder during the reflow process.) The solder joints looked fine—nice, concave fillets. However, the metallographic grain boundaries formed during overheating caused joint failure with very little applied force.

Like in these examples, we can be misled if we don’t understand the science associated with the process. So, we try and minimize voids. What this has come down to in many cases is developing soldering materials and processes that minimize voids. However, there will be voids. If the voids are not acceptable, what then? Are you going to have a battery of rework operators “touching up” void-laden solder joints? Then, it’s back to the X-ray machine.

Voids and Process Capability

Do we challenge the specifications? Should most voids be relegated to the “Process Indicator” category? Should a voiding baseline be established as part of a process capability study? Maybe some lap shear destructive testing should be done as a qualification test. And, if deemed acceptable, use the voiding baseline to compare production results in real time. Then, when a statistically significant negative change in voiding occurs use this to proactively highlight that an assignable cause is entering the process. Even better, if the root cause of the change in voiding can be identified by an automated statistical process control system, the system may be able to make the necessary corrective action in the process without engineering intervention—what we have called Meta Process Control—sometimes called Factory 4.0. The strategic key is to be able to identify voiding changes in production to the capability study baseline in real time, not after 100 boards have been assembled with unacceptable voids.

What We Should Want

The full first line in the song "A Must to Avoid," by Herman's Hermits, is "She's a must to avoid, a complete impossibility."

So, should we require perfect solder joints? Perfectly placed components off the pick and place machine? Zero voiding? Zero in-process defects? Variation in results will take place whether we like it or not. The time the bus arrives at the bus stop everyday will vary in accordance with a normal distribution (i.e., Bell or Gaussian curve). If the variation falls outside the confines of normal distribution it is because a "non-natural" assignable cause has pushed or pulled it. If we require perfection, first know we will never achieve it. Second, we need to ask: At what cost? Does the cost justify the benefit? And, if we end up demanding perfection we need to make sure someone is designated to turn off the lights and close the door when our production business goes out of business.

At least that’s what I think. Hey, what do YOU say? I'd like to hear your thoughts, reactions and opinions. And, please, if you have knowledge and/or experiences concerning the material pricing disparity between products assembled in low and high labor rate regions of the world please contact me.