-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueCreating a Culture of Collaboration
PCB designers could learn quite a bit from NASA and the private companies that develop spacecraft: Every one of these vehicles is a testament to the value of collaboration among disparate stakeholders. Without a collaborative culture, the rocket might never get off the ground.
Breaking High-speed Material Constraints
Do you need specialty materials for your high-speed designs? Maybe not. Improvements in resins mean designers of high-speed boards can sometimes use traditional laminate systems. Learn more in this issue.
Level Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
Calculation of Frequency-Dependent Effective Roughness Dielectric Parameters for Copper Foil Using Equivalent Capacitance Models
January 2, 2019 | Marina Y. Koledintseva, Metamagnetics Inc.*, and Tracey Vincent, CST of AmericaEstimated reading time: 20 minutes
(13)
the corresponding time delay is calculated as,
(14)
The corresponding insertion loss on the line is approximately
(15)
where the total loss constant α for the TEM mode on the line is comprised of the conductor and dielectric loss parts [25],
(16)
and
(17)
Note that herein εr is the dielectric constant (real part of permittivity) of the effective dielectric inside the transmission line, which includes both the substrate dielectric matrix and ERD.
Model Setup for Numerical Simulations
Similar to the previous studies [13], the stripline simulation numerical electromagnetic model has been created. It includes the dielectric matrix material characterization of the substrate dielectric obtained through the extrapolation DERM technique as in [20], [22], and thin layer-like objects representing conductor surface roughness as the ERD: above the trace (“foil” side) and below the trace ("oxide" side). The corresponding ERD layers are also placed on the reference (ground/return) planes. Figure 13 shows a cross-sectional view of the numerical model setup. The line length of the stripline structure was 391.414 mm (15.4 inches); stripline traces were 17.5 mm thick (0.5-oz copper) and 340 mm (13.5 mil) wide. The impedance of the single-ended line was 50 Ω. Cross-sectional dimensions for all the three test lines were identical, except for the foil roughness. Since the length of the modeled line is comparatively long, to make the models more computationally efficient, each model was subdivided into two equal segments, and then cascading of the corresponding ABCD matrices was done.
Figure 13: Numerical model setup.
Numerical Simulations Results with Homogenized Frequency-dependent ERD
The models were simulated using the Finite Integral Technique (FIT), a time domain solver [9]. Time domain solvers are suited to capturing phase results across wide frequency bands. A mesh size in the models was about 2 million cells. The waveguide ports were used for excitation. The measured and modeled data are shown in Figures 14-16. The dielectric parameters of the homogeneous ERD layers in these models are as shown in Figures 9-11. The agreement of the modeled and measured results for all the three test scenarios with STD, VLP, and HVLP foils validate the proposed analytical approach. The high-frequency behavior is captured better as compared to the non-dispersive models as in [13], [14] due to the frequency-dependent DKr and DFr parameters extracted using the equivalent capacitance ERD model.
Figure 14: Measured and modeled S21 results for a stripline structure with STD foil.
Figure 15: Measured and modeled S21 results for a stripline structure with VLP foil.
Figure 16: Measured and modeled S21 results for a stripline structure with HVLP foil.
Numerical Model of Layered ERD Structure
Another way of roughness dielectric numerical modeling was also tested. The “layered” model was set up in the same way as the other models with the only one difference. The foil layer is specified differently from the previous models with homogeneous ERD parameters. In the "layered" model for the STD foil, the roughness dielectric properties are split into three parts: the top 1/3rd part (close to metal) has independent of frequency DKr = 16, the middle 1/3rd part has DKr= 12, and bottom 1/3rd part (next to matrix) has DKr =8. DFr is set as 0.17 in all the three sublayers. In this case, each sublayer is very thin, adding significant mesh count and therefore increasing simulation time.
However, herein, when space mapping for the “layered” model is applied, the object is not split into three separate layers/objects with homogeneous dielectric constants, but the object material properties change depending on the position within the object according to the specified "space map". Note that a "space map" based model does not introduce a new kind of material, but is used to define, for a normal (or anisotropic) material, a generic spatial distribution. This allows for modeling complicated and arbitrary materials. In this work, the ERD itself is specified this way within the matrix material.
In Figure 17, the measured phase is compared to the modeled using “space map” of the ERD layer. The tested cases are the dielectric constants of all three ERD sublayers having first DKr =12; then all of them having DKr =16; and finally, the “layered” roughness dielectric “space map” object with three different DKr values defined consequently. Loss tangent DFr=0.17 in all the layers. Phase results are chosen for comparison because they are the most sensitive to the model parameters choice. As Figure 17 shows, there is an excellent agreement between the measured and the layered model results. From Table 2, the difference between these two results is indeed small (within a few degrees) when compared to the overall phase.
Figure 17: The phase of measured and modeled structures over a narrow frequency band of ~24–26GHz; ERD with DKr=12, with DKr=16, and with space map layered structure.
Table 2: Phase of analytical and layered ERD model at a number of frequencies.
Conclusions
In this work, an analytical model to calculate effective roughness dielectric (ERD) parameters for conductor surface roughness of a PCB foil is presented. Based on the microscopic analysis of the roughness profile, a concentration dependence of metallic inclusions in the transition between the ambient dielectric matrix and copper is obtained. Using such a concentration dependence, the equivalent capacitance associated with the roughness layer is calculated analytically. Then the parameters of the effective roughness dielectric are extracted from this equivalent capacitance. The ERD parameters obtained from the analytical model are frequency dependent unlike in the previous works; therefore, they describe the high-frequency behavior (at data rates of a few dozen Gbps) of PCB interconnects more accurately than the frequency-independent models. The proposed model is applied to three stripline test scenarios with three different types of foils—STD, VLP, and HVLP, and is validated by an excellent agreement between the full-wave FIT numerical modeling and measurements. Two types of numerical models are obtained: using homogeneous effective roughness dielectric and using space mapping when modeling a "layered" ERD. The "layered" ERD provides the closest to the measured result when S21 phases are compared.
References
1. E. Bogatin, D. DeGroot, P.G. Huray, and Y. Shlepnev, “Which one is better? Comparing options to describe frequency dependent losses”, DesignCon 2013, Santa Clara, CA.
2. Y. Shlepnev, “Dielectric and conductor roughness models indentification for successful PCB and packaging interconnect design up to 50 GHz”, The PCB Design Magazine, Feb. 2014, pp. 12-29.
3. L. Simonovich, “Practical method for modeling conductor surface roughness using close packing of equal spheres”, Signal Integrity Journal, July 19, 2016.
4. M.Y. Koledintseva, A. Razmadze, A. Gafarov, S. De, S. Hinaga, and J.L. Drewniak, “PCB conductor surface roughness as a layer with effective material parameters”, IEEE Symp. Electromag. Compat., Pittsburg, PA, 2012, pp. 138- 142.
5. M.Y. Koledintseva, S. Hinaga, and J.L. Drewniak, “Effect of anisotropy on extracted dielectric properties of PCB laminate dielectrics”, IEEE Symp. Electromag. Compat., Long Beach, CA, Aug. 14-19, 2011, Art. No. 6038366, pp. 514-517.
6. M.Y. Koledintseva, T. Vincent, A. Ciccomancini Scogna, and S. Hinaga, “Method of effective roughness dielectric in a PCB: measurement and full-wave simulation verification”, IEEE Trans. Electromag. Compat., vol. 57, no. 4, Aug. 2015, pp. 807-814.
7. M. Koledintseva, T. Vincent, and S. Radu, “Full-wave simulation of an imbalanced differential microstrip line with conductor surface roughness”, IEEE Symp. Electromag. Compat. & Signal Integrity, Santa Clara, CA, March 15-20, 2015, pp. 34-39.
8. M.Y. Koledintseva and T. Vincent, “Comparison of mixed-mode S-parameters in weak and strong coupled differential pairs”, Proc. IEEE Symp. EMC, July 25-30, 2016, Ottawa, Canada, pp. 610-615.
9. CST STUDIO SUITE2017, Dassault Systems Simulia, www.cst.com.
10. T. Vincent, “Simulating dielectric and conductor loss including surface roughness”, iMAPS, 43rd Symp. and Expo, Boxborough, MA, May 2016, http://www.imapsne.org/virtualCDs/2016/2016%20Presentations/A/A4.pdf
11. Simbeor Electromagnetic Signal Integrity Software, www.simberian.com
12. Y. Shlepnev, “How interconnects work: conductor roughness modeling with effective roughness dielectric”, Simbeor® demo-videos. www.simberian.com/
13. T. Vincent, M. Koledintseva, A. Ciccomancini, and S. Hinaga, “Effective roughness dielectric in a PCB: measurement and full-wave simulation verification”, Proc. IEEE Symp. Electromag. Compat., Raleigh, NC, Aug. 3-8, 2014, pp. 798-802.
14. M.Y. Koledintseva, O.Y. Kashurkin, T. Vincent, and S. Hinaga, “Effective roughness dielectric to represent copper foil roughness in printed circuit boards”, DesignCon 2015, Santa Clara, CA, Jan. 27-30, 2015, paper 14-TH4.
15. S. Hinaga, M. Koledintseva, P. Anmula, and J. Drewniak, “Effect of conductor surface roughness upon measured loss and extracted values of PCB laminate material dissipation factor”, Proc. Techn. Conf. IPC Expo/APEX 2009, Mar.31–Apr.2, 2009, Las Vegas, USA, paper S20-2.
16. S. Hinaga, M. Koledintseva, J. Drewniak, A. Koul, and F. Zhou, “Thermal effects on PCB laminate material dielectric constant and dissipation factor”, Techn. Conf. IPC Expo/APEX 2010, Las Vegas, April 5-8, 2010, paper # S16-1.
17. S. De, A.Y. Gafarov, M.Y. Koledintseva, S. Hinaga, R.J. Stanley, and J.L. Drewniak, “Semi-automatic copper foil surface roughness detection from PCB microsection images”, IEEE Symp. Electromag. Compat., Pittsburg, PA, 2012, pp. 132-137.
18. S. Hinaga, S. De, A.Y. Gafarov, M.Y. Koledintseva, and J.L. Drewniak, “Determination of copper foil surface roughness from microsection photographs”, Techn. Conf. IPC Expo/APEX 2012, Las Vegas, Apr. 2012.
19. A.V. Rakov, S. De, M.Y. Koledintseva, S. Hinaga, J.L. Drewniak, and R.J. Stanley, “Quantification of conductor surface roughness profiles in printed circuit boards”, IEEE Trans. Electromag. Compat., vol.57, no. 2, Apr. 2015, pp. 264-273.
20. A. Koul, M.Y. Koledintseva, J.L. Drewniak, and S. Hinaga, “Differential extrapolation method for separating dielectric and rough conductor losses in printed circuit boards”, IEEE Trans. Electromag. Compat., vol. 54, no. 2, pp. 421-433, Apr. 2012.
21. M. Y. Koledintseva, A.V. Rakov, A.I. Koledintsev, J.L. Drewniak, and S. Hinaga, “Elimination of conductor foil roughness effects in characterization of dielectric properties of printed circuit boards”, DesignCon 2014, Santa Clara, CA, Jan. 28-31, 2014, paper 14-TH1.
22. M.Y. Koledintseva, A.V. Rakov, A.I. Koledintsev, J.L. Drewniak, and S. Hinaga, “Improved experiment-based technique to characterize dielectric properties of printed circuit boards”, IEEE Trans. Electromag. Compat., vol. 56, no. 6, Dec. 2014, pp. 1559-1556.
23. Z. Jankovic, M.M. Pavlovich, M.R. Pantovic Pavlovic, M.G. Pavlovic, N.D. Nikolic, J.S. Stevanovic, and S. Prsic, “Electrical and thermal properties of poly(methylmetacrylate) composites filled with electrolytic copper powder”, Int. J. Electrochem. Sci., vol. 13, 2018, pp. 45-57.
24. O.Y. Kashurkin, “Measurements and simulation of conductor-related loss of PCB transmission lines”, M.S.E.E. Thesis, Missouri S&T, 2016.
25. D.M. Pozar, Microwave Engineering, 2nd ed., Wiley, 1998, Chapter 2.
This paper, with original title “Equivalent Capacitance Approach to Obtain Effective Roughness Dielectric Parameters for Copper Foils,” was first presented at the 2018 IPC APEX EXPO Technical Conference and published in the 2018 Technical Conference Proceedings.
* Marina Koledintseva was with Oracle during the writing and presentation of this paper.
Page 4 of 4Suggested Items
Beyond Prepreg: The Glassless ‘Revolution’
06/25/2024 | Marcy LaRont, PCB007 MagazineAs our industry rallies around the call to action for HDI and UHDI, we find unparalleled and myriad laminate options. This abundance is rivaled only by the question surrounding them: Can they measure up to the high technology packaging demands required in our near future? Unsurprisingly, recent developments in FR-4-esque materials for high-speed and high-density designs, as well as newer, glassless technology for replacing traditional glass-impregnated laminates and prepreg, are garnering much interest. I caught up with Alun Morgan, technology ambassador for Ventec International Group, to ask about the impending “glassless revolution” and how it’s poised to solve some of our manufacturing challenges.
Connect the Dots: Designing for Reality—Lamination and Materials
06/19/2024 | Matt Stevenson -- Column: Connect the DotsAs many of you have likely figured out, I am quite passionate about the subject of designing PCBs for the reality of manufacturing. I wrote a book about it and I participate in an I-Connect007 On the Line with… podcast series dedicated to the subject. This companion article will focus on multilayer lamination, keeping the bigger picture in mind: Realistic PCB designs should prioritize manufacturability and reliability of the PCB as well as meet the other design requirements. So, one must account for the production variables associated with individual manufacturing partners.
Day 2: A Full Day at the EIPC Summer Conference
06/19/2024 | Pete Starkey, I-Connect007Editor's note: This is the third and final report from the EIPC Summer Conference. It was a bright and early start to the second day of the 2024 EIPC Summer Conference at the European Space Centre, Noordwijk, The Netherlands, June 4-5. A short journey by bus from the hotel in Leiden and our security passes from the day before got us through the gate and to our seats in the Newton Room for Session 4, “Material Studies,” moderated by Martyn Gaudion.
Looking Into Space: EIPC Summer Conference, Part 2
06/17/2024 | Pete Starkey, I-Connect007“Innovative Development of PCB Technology and Design” was the theme of the second session of the 2024 EIPC Summer Conference, June 4-5, at the European Space Centre, Noordwijk, The Netherlands.