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Zuken Joins UCLA CHIPS ConsortiumJune 6, 2019 | Zuken
Estimated reading time: 2 minutes
Zuken has joined the UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), a collaborative academic / industry research endeavor, to develop solutions to address the challenges associated with the growing demand for computing power in heterogeneous computing environments.
UCLA CHIPS consortium consists of industrial partners from material suppliers, equipment manufacturers, foundries to system integrators, and includes support from universities and government agencies and industrial consortia, working collaboratively to develop new packaging technologies and system architectures and develop the next generation workforce.
Zuken’s role in the consortium is to enable the team at UCLA CHIPS to utilize the system-level design capabilities of CR-8000 to layout and optimize interconnect structures between bare dies on the substrate level, along with using CR-8000 Design Force as part of the engineering curriculum to educate students in learning how to design and solve high-speed issues.
“Classical CMOS scaling has achieved an 3000X reduction in feature size over the last several decades,” explains Profesor Subramanian S. Iyer, Distinguished Professor at the UCLA Electrical and Computer Engineering and director of UCLA CHIPS. “Although it is still continuing, development and manufacturing costs are rising dramatically. At the same time, other aspects of the system such as the package and board miniaturization have not kept up, while the required effort for integrating more and increasingly diverse functions in a SOC approach is growing exponentially.” UCLA CHIPS is, therefore, looking beyond SOC integration at the system level: “At CHIPS we are focused on packaging and system level integration schemes to improve the overall system performance rather than improving the individually packaged components,” says Iyer.
Introducing a Moore’s Law for Packaging
UCLA CHIPS has pioneered the concept of small dielet integration directly on a Silicon-based interconnect fabric (Si IF) or a flexible Fan-out wafer-level Package (FlexTrate). This allows for extremely tight integration of heterogeneous dies leading to a heterogeneous System on Wafer. This also permits us to scale the package significantly—a veritable Moore’s Law for packaging. Inter-die connections may be scaled from BGA pitches of several hundred microns to a few microns and inter-die spacing may be reduced down to 20 mm. This allows for significant improvements in latency, bandwidth and energy per bit over conventional packages.
Through its ability to model and layout complex designs on a system level in 2D and 3D, Zuken’s CR-8000 electronic design environment is ideally suited to model the complex die stack-ups and interposer designs required by the Silicon Interconnect Fabric and FlexTrate paradigms. As part of its corporate commitment to engage with customers in the investigation of new solution approaches, Zuken is providing design tools and services both for the CHIPS initiative and for electrical engineering course work in the UCLA curriculum.
Targeted Solutions For Today’s Complex Product Development Requirements
Humair Mandavia, Chief Strategy Officer and head of Zuken’s SOZO Center in San Jose, California, says, “Our R&D team in San Jose has been established to collaborate more closely with our customers and partners in Silicon Valley and across the US to help identify new technologies and methodologies for hardware design. Our partnership with UCLA CHIPS is another example of this approach that is fruitful for both Zuken and our customers: It puts us into an ideal position to provide more timely and targeted solutions for today’s increasingly complex product development requirements.”
KIC’s Miles Moreau to Present Profiling Basics and Best Practices at SMTA Wisconsin Chapter PCBA Profile Workshop01/25/2024 | KIC
KIC, a renowned pioneer in thermal process and temperature measurement solutions for electronics manufacturing, announces that Miles Moreau, General Manager, will be a featured speaker at the SMTA Wisconsin Chapter In-Person PCBA Profile Workshop.
Panasonic’s Darren Hitchcock spoke with the I-Connect007 Editorial Team on the complexities of moving toward ultra HDI manufacturing. As we learn in this conversation, the number of shifting constraints relative to traditional PCB fabrication is quite large and can sometimes conflict with each other.
In my last column, I discussed cutting-edge innovations in printed circuit board technology, focusing on innovative trends in ultra HDI, embedded passives and components, green PCBs, and advanced substrate materials. This month, I’m following up with the products these new PCB technologies are destined for. Why do we need all these new technologies?
Experience ViTrox's State-of-the-Art Offerings at SMTA Guadalajara 2023 Presented by Sales Channel Partner—SMTo Engineering09/18/2023 | ViTrox
ViTrox, which aims to be the world’s most trusted technology company, is excited to announce that our trusted Sales Channel Partner (SCP) in Mexico, SMTo Engineering, S.A. de C.V., will be participating in SMTA Guadalajara Expo & Tech Forum. They will be exhibiting in Booth #911 from the 25th to the 26th of October 2023, at the Expo Guadalajara in Jalisco, Mexico.
Intel announced one of the industry’s first glass substrates for next-generation advanced packaging, planned for the latter part of this decade.